Trusted Firmware-A Tests, version 2.0
This is the first public version of the tests for the Trusted
Firmware-A project. Please see the documentation provided in the
source tree for more details.
Change-Id: I6f3452046a1351ac94a71b3525c30a4ca8db7867
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Co-authored-by: amobal01 <amol.balasokamble@arm.com>
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Co-authored-by: Asha R <asha.r@arm.com>
Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Co-authored-by: David Cunado <david.cunado@arm.com>
Co-authored-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Co-authored-by: Douglas Raillard <douglas.raillard@arm.com>
Co-authored-by: dp-arm <dimitris.papastamos@arm.com>
Co-authored-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Co-authored-by: Jonathan Wright <jonathan.wright@arm.com>
Co-authored-by: Kévin Petit <kevin.petit@arm.com>
Co-authored-by: Roberto Vargas <roberto.vargas@arm.com>
Co-authored-by: Sathees Balya <sathees.balya@arm.com>
Co-authored-by: Shawon Roy <Shawon.Roy@arm.com>
Co-authored-by: Soby Mathew <soby.mathew@arm.com>
Co-authored-by: Thomas Abraham <thomas.abraham@arm.com>
Co-authored-by: Vikram Kanigiri <vikram.kanigiri@arm.com>
Co-authored-by: Yatharth Kochar <yatharth.kochar@arm.com>
diff --git a/el3_payload/entrypoint.S b/el3_payload/entrypoint.S
new file mode 100644
index 0000000..2da4936
--- /dev/null
+++ b/el3_payload/entrypoint.S
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "arch.h"
+#include "asm_macros.S"
+#include "platform.h"
+
+#define EOT_ASCII_CODE 4
+
+ .data
+welcome_str:
+ .asciz "Booting the EL3 test payload\r\n"
+all_cpus_booted_str:
+ .asciz "All CPUs booted!\r\n"
+
+ .text
+ .global entrypoint
+
+func entrypoint
+ bl mark_cpu_presence
+
+ /* Distinguish primary from secondary CPUs */
+ mrs x0, mpidr_el1
+ ldr x1, =MPIDR_AFFINITY_MASK
+ and x0, x0, x1
+
+ ldr x1, =PRIMARY_CPU_MPID
+ cmp x0, x1
+ b.ne spin_forever
+
+ /*
+ * Only the primary CPU executes the code below
+ */
+
+ adr x0, welcome_str
+ bl print_string
+
+ /* Wait to see each CPU */
+ mov x3, xzr
+1:
+ mov x0, x3
+ bl is_cpu_present
+ cbz x0, 1b
+
+ /* Next CPU, if any */
+ add x3, x3, #1
+ mov x0, #CPUS_COUNT
+ cmp x3, x0
+ b.lt 1b
+
+ /* All CPUs have been detected, announce the good news! */
+ adr x0, all_cpus_booted_str
+ bl print_string
+
+ /* Send EOT (End of Transmission character) character over the UART */
+ mov x0, #EOT_ASCII_CODE
+ bl print_char
+
+spin_forever:
+ wfe
+ b spin_forever
+endfunc entrypoint