diff --git a/plat/amd/versal2/aarch64/plat_helpers.S b/plat/amd/versal2/aarch64/plat_helpers.S
new file mode 100644
index 0000000..715d5f1
--- /dev/null
+++ b/plat/amd/versal2/aarch64/plat_helpers.S
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+	.global platform_get_core_pos
+	.global plat_crash_console_init
+	.global plat_crash_console_flush
+	.global plat_crash_console_putc
+
+/*----------------------------------------------------------------------
+ * unsigned int platform_get_core_pos(u_register_t mpid)
+ *
+ * Function to calculate the core position.
+ *
+ * clobbers: x0 - x3
+ * ---------------------------------------------------------------------
+ */
+func platform_get_core_pos
+	/*
+	 * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
+	 * look as if in a multi-threaded implementation.
+	 */
+	tst	x0, #MPIDR_MT_MASK
+	lsl	x3, x0, #MPIDR_AFFINITY_BITS
+	csel	x3, x3, x0, eq
+
+	/* Extract individual affinity fields from MPIDR */
+	ubfx	x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
+	ubfx	x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
+	ubfx	x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
+
+	/* Compute linear position */
+	mov	x3, #PLATFORM_CORE_COUNT_PER_CLUSTER
+	madd	x1, x2, x3, x1
+	mov	x3, #PLATFORM_MAX_PE_PER_CPU
+	madd	x0, x1, x3, x0
+	ret
+endfunc platform_get_core_pos
+
+	/* ---------------------------------------------
+	 * int plat_crash_console_init(void)
+	 * Function to initialize the crash console
+	 * without a C Runtime to print crash report.
+	 * Clobber list : x0 - x4
+	 * ---------------------------------------------
+	 */
+func plat_crash_console_init
+	mov_imm	x0, CRASH_CONSOLE_BASE
+	mov_imm	x1, PL011_UART_CLK_IN_HZ
+	mov_imm	x2, PL011_BAUDRATE
+	b	console_core_init
+endfunc plat_crash_console_init
+
+	/* ---------------------------------------------
+	 * int plat_crash_console_putc(int c)
+	 * Function to print a character on the crash
+	 * console without a C Runtime.
+	 * Clobber list : x1, x2
+	 * ---------------------------------------------
+	 */
+func plat_crash_console_putc
+	mov_imm	x1, CRASH_CONSOLE_BASE
+	b	console_core_putc
+endfunc plat_crash_console_putc
+
+	/* ---------------------------------------------
+	 * int plat_crash_console_flush()
+	 * Function to force a write of all buffered
+	 * data that hasn't been output.
+	 * Out : return -1 on error else return 0.
+	 * Clobber list : r0 - r1
+	 * ---------------------------------------------
+	 */
+func plat_crash_console_flush
+	mov_imm	x1, CRASH_CONSOLE_BASE
+	b	console_core_flush
+endfunc plat_crash_console_flush
diff --git a/plat/amd/versal2/include/platform_def.h b/plat/amd/versal2/include/platform_def.h
new file mode 100644
index 0000000..645a5eb
--- /dev/null
+++ b/plat/amd/versal2/include/platform_def.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <arch.h>
+
+#define PLATFORM_LINKER_FORMAT			"elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH			aarch64
+
+#define TFTF_BASE				U(0x8000000)
+
+#define CACHE_WRITEBACK_GRANULE			U(0x40)
+
+#define PLATFORM_CLUSTER_COUNT			U(4)
+#define PLATFORM_CORE_COUNT_PER_CLUSTER		U(2)
+#define PLATFORM_MAX_PE_PER_CPU			U(1)
+/* Because of make_mpid from include/lib/tftf_lib.h */
+#define PLAT_MAX_PE_PER_CPU		PLATFORM_MAX_PE_PER_CPU
+
+#define PLATFORM_CORE_COUNT			(PLATFORM_CLUSTER_COUNT * \
+						PLATFORM_CORE_COUNT_PER_CLUSTER)
+#define PLATFORM_NUM_AFFS			(PLATFORM_CORE_COUNT + \
+						PLATFORM_CLUSTER_COUNT + 1)
+#define PLATFORM_MAX_AFFLVL			MPIDR_AFFLVL2
+#define PLAT_MAX_PWR_LEVEL			MPIDR_AFFLVL2
+#define PLAT_MAX_PWR_STATES_PER_LVL		U(2)
+
+
+#define PLATFORM_STACK_SIZE			U(0x440)
+#define PCPU_DV_MEM_STACK_SIZE			U(0x440)
+
+
+#define PLAT_VIRT_ADDR_SPACE_SIZE		(1ULL << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE		(1ULL << 32)
+#define MAX_XLAT_TABLES				U(8)
+#define MAX_MMAP_REGIONS			U(16)
+
+#define DRAM_BASE				U(0x0)
+#define DRAM_SIZE				U(0x80000000)
+
+/*
+ * TFTF_NVM_OFFSET/SIZE correspond to the NVM partition in the partition
+ * table
+ */
+#define TFTF_NVM_SIZE				U(0x600000)
+#define TFTF_NVM_OFFSET				U(0x20000000)
+
+/* Local state bit width for each level in the state-ID field of power state */
+#define PLAT_LOCAL_PSTATE_WIDTH			U(4)
+
+/* GIC related addresses from datasheet */
+#define GICD_REG_BASE				U(0xe2000000)
+#define GICR_REG_BASE				U(0xe2060000)
+
+/* GICv3 is used, dummy definition to resolve build failure */
+#define GICC_REG_BASE				U(0xe2000000)
+
+/*
+ * Memory mapped devices that we must create MMU mappings for them
+ */
+#define GIC_BASE				GICD_REG_BASE
+#define GIC_SIZE				U(0x01000000)
+
+#define TTC_BASE				U(0xF1E70000)
+#define TTC_SIZE				U(0x00010000)
+
+#define SYS_CNT_BASE1				TTC_BASE
+#define SYS_CNT_SIZE				TTC_SIZE
+
+#define LPD_IOU_SLCR				U(0xEB410000)
+#define LPD_IOU_SLCR_SIZE			U(0x00010000)
+
+/* ARM PL011 UART */
+#define PL011_UART0_BASE			U(0xf1920000)
+#define PL011_BAUDRATE				U(115200)
+#define PL011_UART_CLK_IN_HZ			U(100000000)
+
+#define PLAT_ARM_UART_BASE                      PL011_UART0_BASE
+#define PLAT_ARM_UART_SIZE                      U(0x1000)
+
+#define CRASH_CONSOLE_BASE			PL011_UART0_BASE
+#define CRASH_CONSOLE_SIZE			PLAT_ARM_UART_SIZE
+
+/*******************************************************************************
+ * Non-Secure Software Generated Interrupts IDs
+ ******************************************************************************/
+#define IRQ_NS_SGI_0				0
+#define IRQ_NS_SGI_1				1
+#define IRQ_NS_SGI_2				2
+#define IRQ_NS_SGI_3				3
+#define IRQ_NS_SGI_4				4
+#define IRQ_NS_SGI_5				5
+#define IRQ_NS_SGI_6				6
+#define IRQ_NS_SGI_7				7
+
+/* Per-CPU Hypervisor Timer Interrupt ID */
+#define IRQ_PCPU_HP_TIMER			U(29)
+/* Datasheet: TIME00 event*/
+#define IRQ_CNTPSIRQ1				U(29)
+
+/* Refer to AM011(v1.5), Chapter 50, Page 430 */
+#define PLAT_MAX_SPI_OFFSET_ID			U(223)
+
+/*
+ * Times(in ms) used by test code for completion of different events.
+ */
+#define PLAT_SUSPEND_ENTRY_TIME			U(15)
+#define PLAT_SUSPEND_ENTRY_EXIT_TIME		U(30)
+
+/*
+ * Dummy definitions that we need just to compile...
+ */
+#define ARM_SECURE_SERVICE_BUFFER_BASE		U(0)
+#define ARM_SECURE_SERVICE_BUFFER_SIZE		U(100)
+
+/* LPD_SWDT_INT, AM011(v1.5), Chapter 50, Page 428 */
+#define IRQ_TWDOG_INTID				U(0x51)
+
+#define TTC_TIMER_IRQ				U(75)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/amd/versal2/platform.mk b/plat/amd/versal2/platform.mk
new file mode 100644
index 0000000..2304d2f
--- /dev/null
+++ b/plat/amd/versal2/platform.mk
@@ -0,0 +1,29 @@
+#
+# Copyright (c) 2024, Advanced Micro Devices, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+XLNX_COMMON_PATH :=	plat/xilinx/common
+VERSAL2_PATH :=	plat/amd/versal2
+
+PLAT_INCLUDES	:=	-I${XLNX_COMMON_PATH}/include/			\
+			-I${VERSAL2_PATH}/include/
+
+PLAT_SOURCES	:=	drivers/arm/gic/arm_gic_v2v3.c                  \
+			drivers/arm/gic/gic_common.c                    \
+			drivers/arm/gic/gic_v2.c                        \
+			drivers/arm/gic/gic_v3.c                        \
+			drivers/arm/pl011/${ARCH}/pl011_console.S       \
+			drivers/arm/timer/private_timer.c		\
+			drivers/console/console.c                       \
+			${VERSAL2_PATH}/versal2_setup.c		\
+			${VERSAL2_PATH}/versal2_pwr_state.c	\
+			${VERSAL2_PATH}/aarch64/plat_helpers.S	\
+			${XLNX_COMMON_PATH}/timer/timers.c
+
+PLAT_TESTS_SKIP_LIST    := ${VERSAL2_PATH}/tests_to_skip.txt
+
+ifeq ($(USE_NVM),1)
+$(error "Versal2 port of TFTF doesn't currently support USE_NVM=1")
+endif
diff --git a/plat/amd/versal2/tests_to_skip.txt b/plat/amd/versal2/tests_to_skip.txt
new file mode 100644
index 0000000..2c286ec
--- /dev/null
+++ b/plat/amd/versal2/tests_to_skip.txt
@@ -0,0 +1,64 @@
+#
+# Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+################################################################################
+# Disable the listed tests for Versal2 Platform.
+################################################################################
+#TESTS: tftf-validation
+Framework Validation/Events API
+Framework Validation/NVM serialisation
+
+#TESTS: Timer framework Validation
+Timer framework Validation
+
+#TESTS: Boot requirement tests
+Boot requirement tests
+
+ARM_ARCH_SVC
+PMU Leakage
+
+#TESTS: CPU extensions
+CPU extensions/PMUv3 SMC counter preservation
+
+#TESTS: Performance tests
+Performance tests/Test cluster power up latency
+
+#TESTS: FF-A
+FF-A Setup and Discovery/FF-A RXTX unmap SP rxtx buffer
+FF-A Setup and Discovery/Test FFA_PARTITION_INFO_GET v1.0
+FF-A Memory Sharing/Lend memory, clear flag set
+SIMD,SVE Registers context/Check that SIMD registers context is preserved
+FF-A Interrupt
+FF-A Notifications
+
+#TESTS: AMD-Xilinx tests
+AMD-Xilinx tests
+
+#TESTS: psci
+PSCI Affinity Info/Affinity info level0 powerdown
+PSCI CPU Suspend/CPU suspend to powerdown at level 0
+PSCI CPU Suspend/CPU suspend to powerdown at level 1
+PSCI CPU Suspend/CPU suspend to powerdown at level 2
+PSCI CPU Suspend/CPU suspend to standby at level 0
+PSCI CPU Suspend/CPU suspend to standby at level 1
+PSCI CPU Suspend/CPU suspend to standby at level 2
+PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 0 in OSI mode
+PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 1 in OSI mode
+PSCI System Suspend Validation/System suspend multiple times
+PSCI System Suspend Validation/system suspend from all cores
+PSCI System Suspend Validation/Validate suspend to RAM functionality
+PSCI System Suspend Validation/Validate PSCI System Suspend API
+
+#PSCI
+PSCI Features
+PSCI CPU Suspend in OSI mode
+
+#Query runtime services
+Query runtime services/Query Vendor-Specific Service
+Query runtime services/Probe PMF Version
+
+#TESTS: el3-power-state
+EL3 power state parser validation
diff --git a/plat/amd/versal2/versal2_pwr_state.c b/plat/amd/versal2/versal2_pwr_state.c
new file mode 100644
index 0000000..a9bff07
--- /dev/null
+++ b/plat/amd/versal2/versal2_pwr_state.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+
+#include <arch.h>
+#include <platform.h>
+#include <psci.h>
+
+/*
+ * State IDs for local power states.
+ */
+#define VERSAL2_RETENTION_STATE_ID	1	/* Valid for only CPUs */
+#define VERSAL2_OFF_STATE_ID		0	/* Valid for CPUs and Clusters */
+
+/*
+ * Suspend depth definitions for each power state
+ */
+typedef enum {
+	VERSAL2_RUN_DEPTH = 0,
+	VERSAL2_RETENTION_DEPTH,
+	VERSAL2_OFF_DEPTH,
+} suspend_depth_t;
+
+/* The state property array with details of idle state possible for the core */
+static const plat_state_prop_t core_state_prop[] = {
+	{VERSAL2_RETENTION_DEPTH, VERSAL2_RETENTION_STATE_ID, PSTATE_TYPE_STANDBY},
+	{VERSAL2_OFF_DEPTH, VERSAL2_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+	{0},
+};
+
+/* The state property array with details of idle state possible for the cluster */
+static const plat_state_prop_t cluster_state_prop[] = {
+	{VERSAL2_OFF_DEPTH, VERSAL2_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+	{0},
+};
+
+/* The state property array with details of idle state possible for the system level */
+static const plat_state_prop_t system_state_prop[] = {
+	{VERSAL2_OFF_DEPTH, VERSAL2_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+	{0},
+};
+
+const plat_state_prop_t *plat_get_state_prop(unsigned int level)
+{
+	switch (level) {
+	case MPIDR_AFFLVL0:
+		return core_state_prop;
+	case MPIDR_AFFLVL1:
+		return cluster_state_prop;
+	case MPIDR_AFFLVL2:
+		return system_state_prop;
+	default:
+		return NULL;
+	}
+}
diff --git a/plat/amd/versal2/versal2_setup.c b/plat/amd/versal2/versal2_setup.c
new file mode 100644
index 0000000..0db69d6
--- /dev/null
+++ b/plat/amd/versal2/versal2_setup.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <arch.h>
+#include <drivers/arm/arm_gic.h>
+#include <drivers/console.h>
+#include <platform.h>
+#include <tftf_lib.h>
+
+#include <platform_def.h>
+#include <util.h>
+
+static const struct {
+	unsigned int cluster_id;
+	unsigned int cpu_id;
+} versal2_cores[PLATFORM_CORE_COUNT] = {
+	CLUSTER_DEF(0),
+	CLUSTER_DEF(1),
+	CLUSTER_DEF(2),
+	CLUSTER_DEF(3)
+};
+
+
+static const mmap_region_t mmap[] = {
+	MAP_REGION_FLAT(DRAM_BASE + TFTF_NVM_OFFSET, TFTF_NVM_SIZE, MT_MEMORY | MT_RW | MT_NS),
+	MAP_REGION_FLAT(GIC_BASE, GIC_SIZE, MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(CRASH_CONSOLE_BASE, CRASH_CONSOLE_SIZE, MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(TTC_BASE, TTC_SIZE, MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(LPD_IOU_SLCR, LPD_IOU_SLCR_SIZE, MT_DEVICE | MT_RW | MT_NS),
+	{0}
+};
+
+/* Power Domain Tree Descriptor array */
+const unsigned char versal2_pwr_tree_desc[] = {
+	/* Number of root nodes */
+	1,
+	/* Number of clusters */
+	PLATFORM_CLUSTER_COUNT,
+	/* Number of children for the first cluster node */
+	PLATFORM_CORE_COUNT_PER_CLUSTER,
+	/* Number of children for the second cluster node */
+	PLATFORM_CORE_COUNT_PER_CLUSTER,
+	/* Number of children for the third cluster node */
+	PLATFORM_CORE_COUNT_PER_CLUSTER,
+	/* Number of children for the fourth cluster node */
+	PLATFORM_CORE_COUNT_PER_CLUSTER
+};
+
+
+const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
+{
+	return versal2_pwr_tree_desc;
+}
+
+/*
+ * Generate the MPID from the core position.
+ */
+uint64_t tftf_plat_get_mpidr(unsigned int core_pos)
+{
+	assert(core_pos < PLATFORM_CORE_COUNT);
+
+	return (uint64_t)make_mpid(versal2_cores[core_pos].cluster_id,
+				versal2_cores[core_pos].cpu_id);
+}
+
+void tftf_plat_arch_setup(void)
+{
+	tftf_plat_configure_mmu();
+}
+
+void tftf_early_platform_setup(void)
+{
+	console_init(CRASH_CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
+}
+
+void tftf_platform_setup(void)
+{
+	arm_gic_init(GICC_REG_BASE, GICD_REG_BASE, GICR_REG_BASE);
+	arm_gic_setup_global();
+	arm_gic_setup_local();
+}
+
+const mmap_region_t *tftf_platform_get_mmap(void)
+{
+	return mmap;
+}
diff --git a/plat/xilinx/common/include/util.h b/plat/xilinx/common/include/util.h
new file mode 100644
index 0000000..c6d16ce
--- /dev/null
+++ b/plat/xilinx/common/include/util.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef UTIL_H
+#define UTIL_H
+
+#include <platform_def.h>
+
+#define CPU_DEF(cluster, cpu)	{ cluster, cpu }
+
+#if (PLATFORM_CORE_COUNT_PER_CLUSTER == 1U)
+#define CLUSTER_DEF(cluster)	\
+	CPU_DEF(cluster, 0)
+#elif (PLATFORM_CORE_COUNT_PER_CLUSTER == 2U)
+#define CLUSTER_DEF(cluster)	\
+	CPU_DEF(cluster, 0),		\
+	CPU_DEF(cluster, 1)
+#elif (PLATFORM_CORE_COUNT_PER_CLUSTER == 4U)
+#define CLUSTER_DEF(cluster)	\
+	CPU_DEF(cluster, 0),		\
+	CPU_DEF(cluster, 1),		\
+	CPU_DEF(cluster, 2),		\
+	CPU_DEF(cluster, 3)
+#endif
+
+#endif /* UTIL_H */
diff --git a/plat/xilinx/common/timer/timers.c b/plat/xilinx/common/timer/timers.c
index f53cd84..a6e1afa 100644
--- a/plat/xilinx/common/timer/timers.c
+++ b/plat/xilinx/common/timer/timers.c
@@ -27,6 +27,7 @@
 
 #define TTC_CNT_CNTRL_DISABLE_MASK	BIT(0)
 
+#define TTC_CLK_SEL_OFFSET		U(0x360)
 #define TTC_CLK_SEL_MASK		GENMASK(1, 0)
 
 #define TTC_CLK_SEL_PS_REF		BIT(0)
diff --git a/tftf/tests/plat/amd/versal2/test_all_cores.c b/tftf/tests/plat/amd/versal2/test_all_cores.c
new file mode 100644
index 0000000..d7342bf
--- /dev/null
+++ b/tftf/tests/plat/amd/versal2/test_all_cores.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <events.h>
+#include <plat_topology.h>
+#include <platform.h>
+#include <power_management.h>
+#include <psci.h>
+#include <test_helpers.h>
+#include <tftf_lib.h>
+#include <timer.h>
+
+static event_t cpu_has_entered_test[PLATFORM_CORE_COUNT];
+
+/*
+ * Test entry point function for non-lead CPUs.
+ * Specified by the lead CPU when bringing up other CPUs.
+ */
+static test_result_t non_lead_cpu_fn(void)
+{
+	unsigned int mpid = read_mpidr_el1() & MPID_MASK;
+	unsigned int core_pos = platform_get_core_pos(mpid);
+
+	VERBOSE("%s\n", __func__);
+
+	/* Signal to the lead CPU that the calling CPU has entered the test */
+	tftf_send_event(&cpu_has_entered_test[core_pos]);
+
+	return TEST_RESULT_SUCCESS;
+}
+
+/*
+ * @Test_Aim@ Code for a test running on multiple CPUs.
+ *
+ * This "test" powers on all CPUs on the platform and report test success.
+ * The function test_multi_core() runs on the lead CPU only.
+ * The test entrypoint for other CPUs is non_lead_cpu_fn(), as specified when
+ * bringing them up.
+ * 1) Power on all secondary cores
+ * 2) after a delay power off all secondary cores
+ *
+ * The test is skipped if an error occurs during the bring-up of non-lead CPUs.
+ */
+test_result_t test_power_on_cores(void)
+{
+	unsigned int lead_mpid;
+	unsigned int cpu_mpid, cpu_node;
+	unsigned int core_pos;
+	int psci_ret;
+
+	lead_mpid = read_mpidr_el1() & MPID_MASK;
+
+	VERBOSE("%s: lead_mpid = 0x%x\n", __func__, lead_mpid);
+
+	SKIP_TEST_IF_LESS_THAN_N_CPUS(2);
+
+	/* Power on all CPUs */
+	for_each_cpu(cpu_node) {
+		cpu_mpid = tftf_get_mpidr_from_node(cpu_node);
+		/* Skip lead CPU as it is already powered on */
+		if (cpu_mpid == lead_mpid)
+			continue;
+
+		VERBOSE("%s getting cpu_mpid = 0x%x powered on\n", __func__,
+				cpu_mpid);
+		psci_ret = tftf_cpu_on(cpu_mpid, (uintptr_t) non_lead_cpu_fn, 0);
+		if (psci_ret != PSCI_E_SUCCESS) {
+			tftf_testcase_printf("Failed to power on CPU 0x%x (%d)\n",
+					cpu_mpid, psci_ret);
+			/*return TEST_RESULT_SKIPPED; */
+		}
+	}
+
+	/* Wait for non-lead CPUs to enter the test */
+	for_each_cpu(cpu_node) {
+		cpu_mpid = tftf_get_mpidr_from_node(cpu_node);
+		/* Skip lead CPU */
+		if (cpu_mpid == lead_mpid)
+			continue;
+
+		core_pos = platform_get_core_pos(cpu_mpid);
+		tftf_wait_for_event(&cpu_has_entered_test[core_pos]);
+	}
+
+	return TEST_RESULT_SUCCESS;
+}
diff --git a/tftf/tests/tests-versal2.mk b/tftf/tests/tests-versal2.mk
new file mode 100644
index 0000000..a76fdb7
--- /dev/null
+++ b/tftf/tests/tests-versal2.mk
@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2024, Advanced Micro Devices, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+TESTS_SOURCES   +=      $(addprefix tftf/tests/plat/amd/versal2/,          \
+	        test_all_cores.c                                           \
+		)
diff --git a/tftf/tests/tests-versal2.xml b/tftf/tests/tests-versal2.xml
new file mode 100644
index 0000000..1a47586
--- /dev/null
+++ b/tftf/tests/tests-versal2.xml
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!--
+  Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+
+  SPDX-License-Identifier: BSD-3-Clause
+-->
+
+<testsuites>
+  <!--
+     The "template" testsuite aims at providing template test code as a
+     starting point for developing new tests. These tests don't do anything
+     useful in terms of testing.
+  -->
+  <testsuite name="Versal2 Tests" description="AMD-Xilinx Versal2 platform test code">
+     <testcase name="Multi core test" function="test_power_on_cores" />
+  </testsuite>
+
+</testsuites>