diff --git a/plat/arm/sgi/common/aarch64/plat_helpers.S b/plat/arm/sgi/common/aarch64/plat_helpers.S
new file mode 100644
index 0000000..056a2f5
--- /dev/null
+++ b/plat/arm/sgi/common/aarch64/plat_helpers.S
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+#include <pl011.h>
+#include <platform_def.h>
+
+	.globl	platform_get_core_pos
+	.globl	plat_crash_console_init
+	.globl	plat_crash_console_putc
+	.globl	plat_crash_console_flush
+
+/*----------------------------------------------------------------------
+ * unsigned int platform_get_core_pos(unsigned long mpid)
+ *
+ * Function to calculate the core position on sgi platforms.
+ *
+ * (ClusterId * SGI_MAX_CPUS_PER_CLUSTER * SGI_MAX_PE_PER_CPU) +
+ * (CPUId * SGI_MAX_PE_PER_CPU) +
+ * ThreadId
+ *
+ * which can be simplified as:
+ *
+ * ((ClusterId * SGI_MAX_CPUS_PER_CLUSTER + CPUId) * SGI_MAX_PE_PER_CPU)
+ * + ThreadId
+ * ---------------------------------------------------------------------
+ */
+func platform_get_core_pos
+	/*
+	 * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
+	 * look as if in a multi-threaded implementation.
+	 */
+	tst	x0, #MPIDR_MT_MASK
+	lsl	x3, x0, #MPIDR_AFFINITY_BITS
+	csel	x3, x3, x0, eq
+
+	/* Extract individual affinity fields from MPIDR */
+	ubfx	x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
+	ubfx	x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
+	ubfx	x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
+
+	/* Compute linear position */
+	mov	x3, #SGI_MAX_CPUS_PER_CLUSTER
+	madd	x1, x2, x3, x1
+	mov	x3, #SGI_MAX_PE_PER_CPU
+	madd	x0, x1, x3, x0
+	ret
+endfunc platform_get_core_pos
+
+/* ---------------------------------------------
+ * int plat_crash_console_init(void)
+ * Function to initialize the crash console
+ * without a C Runtime to print crash report.
+ * Clobber list : x0 - x4
+ * ---------------------------------------------
+ */
+func plat_crash_console_init
+	mov_imm	x0, PLAT_ARM_UART_BASE
+	mov_imm	x1, PLAT_ARM_UART_CLK_IN_HZ
+	mov_imm	x2, PL011_BAUDRATE
+	b	console_core_init
+endfunc plat_crash_console_init
+
+/* ---------------------------------------------
+ * int plat_crash_console_putc(int c)
+ * Function to print a character on the crash
+ * console without a C Runtime.
+ * Clobber list : x1, x2
+ * ---------------------------------------------
+ */
+func plat_crash_console_putc
+	mov_imm	x1, PLAT_ARM_UART_BASE
+	b	console_core_putc
+endfunc plat_crash_console_putc
+
+/* ---------------------------------------------
+ * int plat_crash_console_flush()
+ * Function to force a write of all buffered
+ * data that hasn't been output.
+ * Out : return -1 on error else return 0.
+ * Clobber list : r0 - r1
+ * ---------------------------------------------
+ */
+func plat_crash_console_flush
+	mov_imm	x1, PLAT_ARM_UART_BASE
+	b	console_core_flush
+endfunc plat_crash_console_flush
diff --git a/plat/arm/sgi/common/include/sgi_base_platform_def.h b/plat/arm/sgi/common/include/sgi_base_platform_def.h
new file mode 100644
index 0000000..1591f07
--- /dev/null
+++ b/plat/arm/sgi/common/include/sgi_base_platform_def.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SGI_BASE_PLATFORM_DEF_H
+#define SGI_BASE_PLATFORM_DEF_H
+
+#include <arm_def.h>
+
+/* Platform binary types for linking */
+#define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH		aarch64
+
+/*******************************************************************************
+ * Run-time address of the TFTF image.
+ * It has to match the location where the Trusted Firmware-A loads the BL33
+ * image.
+ ******************************************************************************/
+#define TFTF_BASE			0xE0000000
+
+#define SGI_DRAM1_BASE			0x80000000
+#define SGI_DRAM1_SIZE			0x80000000
+#define DRAM_BASE			SGI_DRAM1_BASE
+
+/* TF-A reserves DRAM space 0xFF000000- 0xFFFFFFFF for TZC */
+#define DRAM_SIZE			(SGI_DRAM1_SIZE - 0x1000000)
+
+/* Memory mapped Generic timer interfaces */
+#define SYS_CNT_BASE1			0x2A830000
+
+/* Base address of non-trusted watchdog (SP805) */
+#define SP805_WDOG_BASE			0x1C0F0000
+
+/* Base address and size of external NVM flash */
+#define FLASH_BASE			0x08000000
+
+#define NOR_FLASH_BLOCK_SIZE		0x40000		/* 256KB */
+#define FLASH_SIZE			0x4000000	/* 64MB */
+
+/*
+ * If you want to use DRAM for non-volatile memory then the first 128MB
+ * can be used. However for tests that involve power resets this is not
+ * suitable since the state will be lost.
+ */
+#define TFTF_NVM_OFFSET			0x0
+#define TFTF_NVM_SIZE			0x8000000	/* 128 MB */
+
+/* Sub-system Peripherals */
+#define SGI_DEVICE0_BASE		0x2A000000
+#define SGI_DEVICE0_SIZE		0x26000000
+
+/* Following covers Peripherals and PCIe expansion area */
+#define SGI_DEVICE1_BASE		0x60000000
+#define SGI_DEVICE1_SIZE		0x20000000
+
+/* GIC-600 & interrupt handling related constants */
+#define SGI_GICD_BASE			0x30000000
+#define SGI_GICR_BASE			0x300C0000
+#define SGI_GICC_BASE			0x2C000000
+
+/* SoC's PL011 UART0 related constants */
+#define SGI_PL011_UART0_BASE		0x7FF80000
+#define SGI_PL011_UART0_CLK_IN_HZ	7372800
+
+#define PLAT_ARM_UART_BASE		SGI_PL011_UART0_BASE
+#define PLAT_ARM_UART_CLK_IN_HZ		SGI_PL011_UART0_CLK_IN_HZ
+
+/* Size of cacheable stacks */
+#define PLATFORM_STACK_SIZE		0x1400
+
+/* Size of coherent stacks */
+#define PCPU_DV_MEM_STACK_SIZE		0x600
+
+#define PLATFORM_CORE_COUNT		(SGI_CLUSTER_COUNT * SGI_MAX_CPUS_PER_CLUSTER)
+#define PLATFORM_NUM_AFFS		(SGI_CLUSTER_COUNT + PLATFORM_CORE_COUNT)
+#define PLATFORM_MAX_AFFLVL		MPIDR_AFFLVL1
+
+#define PLAT_MAX_PWR_LEVEL		PLATFORM_MAX_AFFLVL
+#define PLAT_MAX_PWR_STATES_PER_LVL	2
+
+/* I/O Storage NOR flash device */
+#define MAX_IO_DEVICES			1
+#define MAX_IO_HANDLES			1
+
+/* Local state bit width for each level in the state-ID field of power state */
+#define PLAT_LOCAL_PSTATE_WIDTH		4
+
+/* Platform specific page table and MMU setup constants */
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ull << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ull << 32)
+#define MAX_XLAT_TABLES			5
+#define MAX_MMAP_REGIONS		16
+
+/*******************************************************************************
+ * Used to align variables on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ ******************************************************************************/
+#define CACHE_WRITEBACK_SHIFT  		 6
+#define CACHE_WRITEBACK_GRANULE		 (1 << CACHE_WRITEBACK_SHIFT)
+
+/* Non-Secure Software Generated Interupts IDs */
+#define IRQ_NS_SGI_0			0
+#define IRQ_NS_SGI_7			7
+
+/* AP UART1 interrupt is considered as the maximum SPI */
+#define PLAT_MAX_SPI_OFFSET_ID		64
+
+/* AP_REFCLK Generic Timer, Non-secure. */
+#define IRQ_CNTPSIRQ1			92
+
+/* Per-CPU Hypervisor Timer Interrupt ID */
+#define IRQ_PCPU_HP_TIMER		26
+
+/* Times(in ms) used by test code for completion of different events */
+#define PLAT_SUSPEND_ENTRY_TIME		15
+#define PLAT_SUSPEND_ENTRY_EXIT_TIME	30
+
+#endif /* SGI_BASE_PLATFORM_DEF_H */
diff --git a/plat/arm/sgi/common/plat_setup.c b/plat/arm/sgi/common/plat_setup.c
new file mode 100644
index 0000000..211e8d4
--- /dev/null
+++ b/plat/arm/sgi/common/plat_setup.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arm_gic.h>
+#include <xlat_tables_v2.h>
+
+static const mmap_region_t mmap[] = {
+	MAP_REGION_FLAT(SGI_DEVICE0_BASE, SGI_DEVICE0_SIZE,
+			MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(SGI_DEVICE1_BASE, SGI_DEVICE1_SIZE,
+			MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(DRAM_BASE, TFTF_BASE - DRAM_BASE,
+			MT_MEMORY | MT_RW | MT_NS),
+	{0}
+};
+
+const mmap_region_t *tftf_platform_get_mmap(void)
+{
+	return mmap;
+}
+
+void plat_arm_gic_init(void)
+{
+	arm_gic_init(SGI_GICC_BASE, SGI_GICD_BASE, SGI_GICR_BASE);
+}
diff --git a/plat/arm/sgi/common/sgi_common.mk b/plat/arm/sgi/common/sgi_common.mk
new file mode 100644
index 0000000..f19445f
--- /dev/null
+++ b/plat/arm/sgi/common/sgi_common.mk
@@ -0,0 +1,24 @@
+#
+# Copyright (c) 2018, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+PLAT_INCLUDES	:=	-Iplat/arm/sgi/common/include/
+
+PLAT_SOURCES	:=	drivers/arm/gic/arm_gic_v2v3.c			\
+			drivers/arm/gic/gic_v2.c			\
+			drivers/arm/gic/gic_v3.c			\
+			drivers/arm/sp805/sp805.c			\
+			drivers/arm/timer/private_timer.c		\
+			drivers/arm/timer/system_timer.c		\
+			plat/arm/sgi/common/${ARCH}/plat_helpers.S	\
+			plat/arm/sgi/common/plat_setup.c		\
+			plat/arm/sgi/common/sgi_mem_prot.c		\
+			plat/arm/sgi/common/sgi_pwr_state.c
+
+include plat/arm/common/arm_common.mk
+
+ifeq (${USE_NVM},1)
+$(error "USE_NVM is not supported on SGI platforms")
+endif
diff --git a/plat/arm/sgi/common/sgi_mem_prot.c b/plat/arm/sgi/common/sgi_mem_prot.c
new file mode 100644
index 0000000..14da4cd
--- /dev/null
+++ b/plat/arm/sgi/common/sgi_mem_prot.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform.h>
+
+#define SGI_DRAM1_NS_START	(TFTF_BASE + 0x4000000)
+#define SGI_DRAM1_NS_SIZE	0x10000000
+
+static const mem_region_t sgi_ram_ranges[] = {
+	{ SGI_DRAM1_NS_START, SGI_DRAM1_NS_SIZE },
+};
+
+const mem_region_t *plat_get_prot_regions(int *nelem)
+{
+	*nelem = ARRAY_SIZE(sgi_ram_ranges);
+	return sgi_ram_ranges;
+}
diff --git a/plat/arm/sgi/common/sgi_pwr_state.c b/plat/arm/sgi/common/sgi_pwr_state.c
new file mode 100644
index 0000000..305d1f5
--- /dev/null
+++ b/plat/arm/sgi/common/sgi_pwr_state.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform.h>
+#include <psci.h>
+
+/* State IDs for local power states on SGI platforms. */
+#define SGI_PS_RUN_STATE_ID		0 /* Valid for CPUs and Clusters */
+#define SGI_PS_RETENTION_STATE_ID	1 /* Valid for only CPUs */
+#define SGI_PS_OFF_STATE_ID		2 /* Valid for CPUs and Clusters */
+
+/* Suspend depth definitions for each power state */
+#define SGI_PS_RUN_DEPTH	0
+#define SGI_PS_RETENTION_DEPTH	1
+#define SGI_PS_OFF_DEPTH	2
+
+/* The state property array with details of idle state possible for the core */
+static const plat_state_prop_t core_state_prop[] = {
+	{SGI_PS_RETENTION_DEPTH, SGI_PS_RETENTION_STATE_ID,
+		PSTATE_TYPE_STANDBY},
+	{SGI_PS_OFF_DEPTH, SGI_PS_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+	{0},
+};
+
+/* The state property array with details of idle state possible for the cluster */
+static const plat_state_prop_t cluster_state_prop[] = {
+	{SGI_PS_OFF_DEPTH, SGI_PS_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+	{0},
+};
+
+const plat_state_prop_t *plat_get_state_prop(unsigned int level)
+{
+	switch (level) {
+	case MPIDR_AFFLVL0:
+		return core_state_prop;
+	case MPIDR_AFFLVL1:
+		return cluster_state_prop;
+	default:
+		return NULL;
+	}
+}