fix(xilinx): wire Xilinx platforms in docs
Wire Xilinx platform docs to fix build errors when
make DEBUG=1 V=1 doc is called.
Fixes: 30b8bc2aadb8 ("docs(versal-net): add Versal NET documentation")
Fixes: e52f311919f3 ("docs(versal): add versal documentation")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I52f4cf31bec2716a2f8b84a1f01335e387d39556
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
new file mode 100644
index 0000000..6f5d9a5
--- /dev/null
+++ b/docs/plat/index.rst
@@ -0,0 +1,17 @@
+Platform Ports
+==============
+
+.. toctree::
+ :maxdepth: 1
+ :caption: Contents
+ :hidden:
+
+ xilinx-versal_net
+ xilinx-versal
+
+This section provides a list of supported upstream *platform ports* and the
+documentation associated with them.
+
+--------------
+
+*Copyright (c) 2024, Arm Limited. All rights reserved.*