diff --git a/include/lib/pcie/pcie.h b/include/lib/pcie/pcie.h
new file mode 100644
index 0000000..aa3911f
--- /dev/null
+++ b/include/lib/pcie/pcie.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PCIE_H
+#define PCIE_H
+
+#include <cdefs.h>
+#include <stdint.h>
+#include <utils_def.h>
+
+typedef struct {
+	unsigned long ecam_base;	/* ECAM base address */
+	unsigned int segment_num;	/* Segment number of this ECAM */
+	unsigned int start_bus_num;	/* Start bus number for this ECAM space */
+	unsigned int end_bus_num;	/* Last bus number */
+} pcie_info_block_t;
+
+typedef struct {
+	unsigned int num_entries;	/* Number of entries */
+	pcie_info_block_t block[];
+} pcie_info_table_t;
+
+typedef struct {
+	uint32_t bdf;
+	uint32_t rp_bdf;
+} pcie_device_attr_t;
+
+typedef struct __packed {
+	uint32_t num_entries;
+	pcie_device_attr_t device[]; /* in the format of Segment/Bus/Dev/Func */
+} pcie_device_bdf_table_t;
+
+/* Address initialisation structure */
+typedef struct {
+	/* 64 bit prefetchable memory start address */
+	uint64_t bar64_p_start;
+	uint64_t rp_bar64_value;
+	/* 32 bit non-prefetchable memory start address */
+	uint32_t bar32_np_start;
+	/* 32 bit prefetchable memory start address */
+	uint32_t bar32_p_start;
+	uint32_t rp_bar32_value;
+} pcie_bar_init_t;
+
+#define PCIE_EXTRACT_BDF_SEG(bdf)	((bdf >> 24) & 0xFF)
+#define PCIE_EXTRACT_BDF_BUS(bdf)	((bdf >> 16) & 0xFF)
+#define PCIE_EXTRACT_BDF_DEV(bdf)	((bdf >> 8) & 0xFF)
+#define PCIE_EXTRACT_BDF_FUNC(bdf)	(bdf & 0xFF)
+
+/* PCI-compatible region */
+#define PCI_CMP_CFG_SIZE	256
+
+/* PCI Express Extended Configuration Space */
+#define PCIE_CFG_SIZE		4096
+
+#define PCIE_MAX_BUS		256
+#define PCIE_MAX_DEV		32
+#define PCIE_MAX_FUNC		8
+
+#define PCIE_CREATE_BDF(Seg, Bus, Dev, Func)	\
+			((Seg << 24) | (Bus << 16) | (Dev << 8) | Func)
+
+#define PCIE_SUCCESS		0x00000000  /* Operation completed successfully */
+#define PCIE_NO_MAPPING		0x10000001  /* A mapping to a Function does not exist */
+#define PCIE_CAP_NOT_FOUND	0x10000010  /* The specified capability was not found */
+#define PCIE_UNKNOWN_RESPONSE	0xFFFFFFFF  /* Function not found or UR response from completer */
+
+/* Allows storage of 2048 valid BDFs */
+#define PCIE_DEVICE_BDF_TABLE_SZ	8192
+
+typedef enum {
+	HEADER = 0,
+	PCIE_CAP = 1,
+	PCIE_ECAP = 2
+} bitfield_reg_type_t;
+
+typedef enum {
+	HW_INIT = 0,
+	READ_ONLY = 1,
+	STICKY_RO = 2,
+	RSVDP_RO = 3,
+	RSVDZ_RO = 4,
+	READ_WRITE = 5,
+	STICKY_RW = 6
+} bitfield_attr_type_t;
+
+/* Class Code Masks */
+#define CC_SUB_MASK	0xFF	/* Sub Class */
+#define CC_BASE_MASK	0xFF	/* Base Class */
+
+/* Class Code Shifts */
+#define CC_SHIFT	8
+#define CC_SUB_SHIFT	16
+#define CC_BASE_SHIFT	24
+
+void pcie_create_info_table(void);
+pcie_device_bdf_table_t *pcie_get_bdf_table(void);
+uint32_t pcie_find_capability(uint32_t bdf, uint32_t cid_type, uint32_t cid,
+				uint32_t *cid_offset);
+uint32_t pcie_read_cfg(uint32_t bdf, uint32_t offset);
+void pcie_write_cfg(uint32_t bdf, uint32_t offset, uint32_t data);
+
+#endif /* PCIE_H */
diff --git a/include/lib/pcie/pcie_doe.h b/include/lib/pcie/pcie_doe.h
new file mode 100644
index 0000000..4e12afd
--- /dev/null
+++ b/include/lib/pcie/pcie_doe.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2024, Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PCIE_DOE_H
+#define PCIE_DOE_H
+
+/* DOE Extended Capability */
+#define DOE_CAP_ID			0x002E
+
+#define DOE_CAP_REG			0x4
+#define DOE_CTRL_REG			0x8
+#define DOE_STATUS_REG			0xC
+#define DOE_WRITE_DATA_MAILBOX_REG	0x10
+#define DOE_READ_DATA_MAILBOX_REG	0x14
+
+#define DOE_CTRL_ABORT_BIT		(1 << 0)
+#define DOE_CTRL_GO_BIT			(1 << 31)
+
+#define DOE_STATUS_BUSY_BIT		(1 << 0)
+#define DOE_STATUS_ERROR_BIT		(1 << 2)
+#define DOE_STATUS_READY_BIT		(1 << 31)
+
+/* Time intervals in ms */
+#define PCI_DOE_TIMEOUT			1000
+#define PCI_DOE_POLL_TIME		10
+
+#define PCI_DOE_POLL_LOOP		(PCI_DOE_TIMEOUT / PCI_DOE_POLL_TIME)
+
+/* DOE Data Object Header 2 Reserved field [31:18] */
+#define PCI_DOE_RESERVED_SHIFT		18
+#define PCI_DOE_RESERVED_MASK		0xFFFC0000
+
+/* Max data object length is 2^18 DW */
+#define PCI_DOE_MAX_LENGTH		(1 << PCI_DOE_RESERVED_SHIFT)
+
+/* SPDM GET_VERSION response DW length */
+#define SPDM_GET_VERS_RESP_LEN						\
+	((sizeof(spdm_version_response_t) +				\
+	(sizeof(spdm_version_number_t) * SPDM_MAX_VERSION_COUNT) +	\
+	(sizeof(uint32_t) - 1)) << 2)
+
+/* PCI-SIG Vendor ID */
+#define PSI_SIG_VENDOR_ID	1
+
+/* Data Object Protocols */
+#define DOE_DISC_PROTOCOL	0
+#define CMA_SPDM_PROTOCOL	1
+#define SEC_CMA_SPDM_PROTOCOL	2
+
+#define DOE_HEADER(_type)	((_type << 16) | PSI_SIG_VENDOR_ID)
+
+#define DOE_HEADER_0		DOE_HEADER(DOE_DISC_PROTOCOL)
+#define DOE_HEADER_1		DOE_HEADER(CMA_SPDM_PROTOCOL)
+#define DOE_HEADER_2		DOE_HEADER(SEC_CMA_SPDM_PROTOCOL)
+#define DOE_HEADER_LENGTH	2
+
+/*
+ * SPDM VERSION structure:
+ * bit[15:12] major_version
+ * bit[11:8]  minor_version
+ * bit[7:4]   update_version_number
+ * bit[3:0]   alpha
+ */
+#define SPDM_VER_MAJOR_SHIFT	12
+#define SPDM_VER_MAJOR_WIDTH	4
+#define SPDM_VER_MINOR_SHIFT	8
+#define SPDM_VER_MINOR_WIDTH	4
+#define SPDM_VER_UPDATE_SHIFT	4
+#define SPDM_VER_UPDATE_WIDTH	4
+#define SPDM_VER_ALPHA_SHIFT	0
+#define SPDM_VER_ALPHA_WIDTH	4
+
+/* DOE Discovery */
+typedef struct {
+	uint8_t index;
+	uint8_t reserved[3];
+} pcie_doe_disc_req_t;
+
+typedef struct {
+	uint16_t vendor_id;
+	uint8_t data_object_type;
+	uint8_t next_index;
+} pcie_doe_disc_resp_t;
+
+void print_doe_disc(pcie_doe_disc_resp_t *data);
+int pcie_doe_send_req(uint32_t header, uint32_t bdf, uint32_t doe_cap_base,
+			uint32_t *req_addr, uint32_t req_len);
+int pcie_doe_recv_resp(uint32_t bdf, uint32_t doe_cap_base,
+			uint32_t *resp_addr, uint32_t *resp_len);
+
+#endif /* PCIE_DOE_H */
diff --git a/include/lib/pcie/pcie_spec.h b/include/lib/pcie/pcie_spec.h
new file mode 100644
index 0000000..31fd98b
--- /dev/null
+++ b/include/lib/pcie/pcie_spec.h
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2024, Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PCIE_SPEC_H
+#define PCIE_SPEC_H
+
+/* Header Type */
+#define TYPE0_HEADER		0
+#define TYPE1_HEADER		1
+
+/* TYPE 0/1 Cmn Cfg reg offsets */
+#define TYPE01_VIDR		0x0
+#define TYPE01_CR		0x4
+#define TYPE01_RIDR		0x8
+#define TYPE01_CLSR		0xc
+#define TYPE01_BAR		0x10
+#define TYPE01_CPR		0x34
+#define TYPE01_ILR		0x3c
+
+/* TYPE 0/1 Cmn Cfg reg shifts and masks */
+#define TYPE01_VIDR_SHIFT	0
+#define TYPE01_VIDR_MASK	0xffff
+#define TYPE01_DIDR_SHIFT	16
+#define TYPE01_DIDR_MASK	0xffff
+#define TYPE01_CCR_SHIFT	8
+#define TYPE01_CCR_MASK		0xffffff
+#define TYPE01_CPR_SHIFT	0
+#define TYPE01_CPR_MASK		0xff
+#define TYPE01_HTR_SHIFT	16
+#define TYPE01_HTR_MASK		0xff
+#define TYPE01_IPR_SHIFT	8
+#define TYPE01_IPR_MASK		0xFF
+#define TYPE01_ILR_SHIFT	0
+#define TYPE01_ILR_MASK		0xFF
+#define TYPE01_BCC_SHIFT	24
+
+#define HB_BASE_CLASS		0x06
+#define HB_SUB_CLASS		0x00
+
+/* Header type reg shifts and masks */
+#define HTR_HL_SHIFT		0x0
+#define HTR_HL_MASK		0x7f
+#define HTR_MFD_SHIFT		7
+#define HTR_MFD_MASK		0x1
+
+/* BAR offset */
+#define BAR0_OFFSET		0x10
+#define BAR_TYPE_0_MAX_OFFSET	0x24
+#define BAR_TYPE_1_MAX_OFFSET	0x14
+#define BAR_NP_TYPE		0x0
+#define BAR_P_TYPE		0x1
+#define BAR_64_BIT		0x1
+#define BAR_32_BIT		0x0
+#define BAR_REG(bar_reg_value)	((bar_reg_value >> 2) & 0x1)
+
+/* Type 1 Cfg reg offsets */
+#define TYPE1_PBN		0x18
+#define TYPE1_SEC_STA		0x1C
+#define TYPE1_NP_MEM		0x20
+#define TYPE1_P_MEM		0x24
+#define TYPE1_P_MEM_BU		0x28	/* Prefetchable Base Upper Offset */
+#define TYPE1_P_MEM_LU		0x2C	/* Prefetchable Limit Upper Offset */
+
+/* Bus Number reg shifts */
+#define SECBN_SHIFT		8
+#define SUBBN_SHIFT		16
+
+/* Bus Number reg masks */
+#define PRIBN_MASK		0xff
+#define SECBN_MASK		0xff
+#define SUBBN_MASK		0xff
+#define SECBN_EXTRACT		0xffff00ff
+
+/* Capability header reg shifts */
+#define PCIE_CIDR_SHIFT		0
+#define PCIE_NCPR_SHIFT		8
+#define PCIE_ECAP_CIDR_SHIFT	0
+#define PCIE_ECAP_NCPR_SHIFT	20
+
+/* Capability header reg masks */
+#define PCIE_CIDR_MASK		0xff
+#define PCIE_NCPR_MASK		0xff
+#define PCIE_ECAP_CIDR_MASK	0xffff
+#define PCIE_ECAP_NCPR_MASK	0xfff
+
+#define PCIE_CAP_START		0x40
+#define PCIE_CAP_END		0xFC
+#define PCIE_ECAP_START		0x100
+#define PCIE_ECAP_END		0xFFC
+
+/* Capability Structure IDs */
+#define CID_PCIECS		0x10
+#define CID_MSI			0x05
+#define CID_MSIX		0x11
+#define CID_PMC			0x01
+#define CID_EA			0x14
+#define ECID_AER		0x0001
+#define ECID_RCECEA		0x0007
+#define ECID_ACS		0x000D
+#define ECID_ARICS		0x000E
+#define ECID_ATS		0x000F
+#define ECID_PRI		0x0013
+#define ECID_PASID		0x001B
+#define ECID_DPC		0x001D
+#define ECID_DVSEC		0x0023
+
+/* PCI Express capability struct offsets */
+#define CIDR_OFFSET		0x0
+#define PCIECR_OFFSET		0x2
+#define DCAPR_OFFSET		0x4
+#define ACSCR_OFFSET		0x4
+#define DCTLR_OFFSET		0x8
+#define LCAPR_OFFSET		0xC
+#define LCTRLR_OFFSET		0x10
+#define DCAP2R_OFFSET		0x24
+#define DCTL2R_OFFSET		0x28
+#define DCTL2R_MASK		0xFFFF
+#define LCAP2R_OFFSET		0x2C
+#define LCTL2R_OFFSET		0x30
+#define DCTL2R_MASK		0xFFFF
+#define DSTS_SHIFT		16
+#define DS_UNCORR_MASK		0x6
+#define DS_CORR_MASK		0x1
+
+/* PCIe capabilities reg shifts and masks */
+#define PCIECR_DPT_SHIFT	4
+#define PCIECR_DPT_MASK		0xf
+
+/* Device bitmask definitions */
+#define RCiEP			(1 << 0b1001)
+#define RCEC			(1 << 0b1010)
+#define EP			(1 << 0b0000)
+#define RP			(1 << 0b0100)
+#define UP			(1 << 0b0101)
+#define DP			(1 << 0b0110)
+#define iEP_EP			(1 << 0b1100)
+#define iEP_RP			(1 << 0b1011)
+#define PCI_PCIE		(1 << 0b1000)
+#define PCIE_PCI		(1 << 0b0111)
+#define PCIe_ALL		(iEP_RP | iEP_EP | RP | EP | RCEC | RCiEP)
+
+#endif /* PCIE_SPEC_H */
diff --git a/lib/pcie/pcie.c b/lib/pcie/pcie.c
new file mode 100644
index 0000000..22464c2
--- /dev/null
+++ b/lib/pcie/pcie.c
@@ -0,0 +1,599 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <debug.h>
+#include <mmio.h>
+#include <stddef.h>
+#include <pcie.h>
+#include <pcie_spec.h>
+#include <tftf_lib.h>
+
+#include <platform_pcie.h>
+
+#define PCIE_DEBUG	VERBOSE
+
+const pcie_info_table_t *g_pcie_info_table;
+pcie_device_bdf_table_t *g_pcie_bdf_table;
+
+pcie_device_bdf_table_t pcie_bdf_table[PCIE_DEVICE_BDF_TABLE_SZ];
+
+uintptr_t pcie_cfg_addr(uint32_t bdf)
+{
+	uint32_t bus = PCIE_EXTRACT_BDF_BUS(bdf);
+	uint32_t dev = PCIE_EXTRACT_BDF_DEV(bdf);
+	uint32_t func = PCIE_EXTRACT_BDF_FUNC(bdf);
+	uint32_t segment = PCIE_EXTRACT_BDF_SEG(bdf);
+	uint32_t cfg_addr;
+	uintptr_t ecam_base = 0;
+	unsigned int i = 0;
+
+	assert((bus < PCIE_MAX_BUS) && (dev < PCIE_MAX_DEV) && (func < PCIE_MAX_FUNC));
+	assert(g_pcie_info_table != NULL);
+
+	while (i < g_pcie_info_table->num_entries) {
+		/* Derive ECAM specific information */
+		const pcie_info_block_t *block = &g_pcie_info_table->block[i];
+
+		if ((bus >= block->start_bus_num) &&
+			(bus <= block->end_bus_num) &&
+			(segment == block->segment_num)) {
+			ecam_base = block->ecam_base;
+			break;
+		}
+		i++;
+	}
+
+	assert(ecam_base != 0);
+
+	/*
+	 * There are 8 functions / device
+	 * 32 devices / Bus and each has a 4KB config space
+	 */
+	cfg_addr = (bus * PCIE_MAX_DEV * PCIE_MAX_FUNC * PCIE_CFG_SIZE) +
+		(dev * PCIE_MAX_FUNC * PCIE_CFG_SIZE) + (func * PCIE_CFG_SIZE);
+
+	return ecam_base + cfg_addr;
+}
+
+/*
+ * @brief  This API reads 32-bit data from PCIe config space pointed by Bus,
+ *	   Device, Function and register offset.
+ *	   1. Caller       -  Test Suite
+ *	   2. Prerequisite -  pcie_create_info_table
+ * @param  bdf    - concatenated Bus(8-bits), device(8-bits) & function(8-bits)
+ * @param  offset - Register offset within a device PCIe config space
+ *
+ * @return  32-bit data read from the config space
+ */
+uint32_t pcie_read_cfg(uint32_t bdf, uint32_t offset)
+{
+	uintptr_t addr = pcie_cfg_addr(bdf);
+
+	return mmio_read_32(addr + offset);
+}
+
+/*
+ * @brief  This API writes 32-bit data to PCIe config space pointed by Bus,
+ *	   Device, Function and register offset.
+ *	   1. Caller       -  Test Suite
+ *	   2. Prerequisite -  val_pcie_create_info_table
+ * @param  bdf    - concatenated Bus(8-bits), device(8-bits) & function(8-bits)
+ * @param  offset - Register offset within a device PCIe config space
+ * @param  data   - data to be written to the config space
+ *
+ * @return  None
+ */
+void pcie_write_cfg(uint32_t bdf, uint32_t offset, uint32_t data)
+{
+	uintptr_t addr = pcie_cfg_addr(bdf);
+
+	mmio_write_32(addr + offset, data);
+}
+
+/*
+ * @brief   Check if BDF is PCIe Host Bridge.
+ *
+ * @param   bdf - Function's Segment/Bus/Dev/Func in PCIE_CREATE_BDF format
+ * @return  false If not a Host Bridge, true If it's a Host Bridge.
+ */
+bool pcie_is_host_bridge(uint32_t bdf)
+{
+	uint32_t reg_value = pcie_read_cfg(bdf, TYPE01_RIDR);
+
+	if ((HB_BASE_CLASS == ((reg_value >> CC_BASE_SHIFT) & CC_BASE_MASK)) &&
+		(HB_SUB_CLASS == ((reg_value >> CC_SUB_SHIFT) & CC_SUB_MASK))) {
+		return true;
+	}
+
+	return false;
+}
+
+/*
+ * @brief  Find a Function's config capability offset matching it's input parameter
+ *	   cid. cid_offset set to the matching cpability offset w.r.t. zero.
+ *
+ * @param  bdf        - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF
+ * @param  cid        - Capability ID
+ * @param  cid_offset - On return, points to cid offset in Function config space
+ * @return PCIE_CAP_NOT_FOUND, if there was a failure in finding required capability.
+ *	   PCIE_SUCCESS, if the search was successful.
+ */
+uint32_t pcie_find_capability(uint32_t bdf, uint32_t cid_type, uint32_t cid,
+				uint32_t *cid_offset)
+{
+	uint32_t reg_value, next_cap_offset;
+
+	if (cid_type == PCIE_CAP) {
+		/* Search in PCIe configuration space */
+		reg_value = pcie_read_cfg(bdf, TYPE01_CPR);
+
+		next_cap_offset = (reg_value & TYPE01_CPR_MASK);
+		while (next_cap_offset != 0) {
+			reg_value = pcie_read_cfg(bdf, next_cap_offset);
+			if ((reg_value & PCIE_CIDR_MASK) == cid) {
+				*cid_offset = next_cap_offset;
+				return PCIE_SUCCESS;
+			}
+			next_cap_offset = ((reg_value >> PCIE_NCPR_SHIFT) &
+						PCIE_NCPR_MASK);
+		}
+	} else if (cid_type == PCIE_ECAP) {
+		/* Search in PCIe extended configuration space */
+		next_cap_offset = PCIE_ECAP_START;
+		while (next_cap_offset != 0) {
+			reg_value = pcie_read_cfg(bdf, next_cap_offset);
+			if ((reg_value & PCIE_ECAP_CIDR_MASK) == cid) {
+				*cid_offset = next_cap_offset;
+				return PCIE_SUCCESS;
+			}
+			next_cap_offset = ((reg_value >> PCIE_ECAP_NCPR_SHIFT) &
+						PCIE_ECAP_NCPR_MASK);
+		}
+	}
+
+	/* The capability was not found */
+	return PCIE_CAP_NOT_FOUND;
+}
+
+/*
+ * @brief  This API is used as placeholder to check if the bdf
+ *	   obtained is valid or not
+ *
+ * @param  bdf
+ * @return true if bdf is valid else false
+ */
+bool pcie_check_device_valid(uint32_t bdf)
+{
+	(void) bdf;
+	/*
+	 * Add BDFs to this function if PCIe tests
+	 * need to be ignored for a BDF for any reason
+	 */
+	return true;
+}
+
+/*
+ * @brief  Returns whether a PCIe Function is an on-chip peripheral or not
+ *
+ * @param  bdf	   - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF
+ * @return Returns TRUE if the Function is on-chip peripheral, FALSE if it is
+ *	   not an on-chip peripheral
+ */
+bool pcie_is_onchip_peripheral(uint32_t bdf)
+{
+	(void)bdf;
+	return false;
+}
+
+/*
+ * @brief  Returns the type of pcie device or port for the given bdf
+ *
+ * @param  bdf     - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF
+ * @return Returns (1 << 0b1001) for RCiEP,  (1 << 0b1010) for RCEC,
+ *		   (1 << 0b0000) for EP,     (1 << 0b0100) for RP,
+ *		   (1 << 0b1100) for iEP_EP, (1 << 0b1011) for iEP_RP,
+ *		   (1 << PCIECR[7:4]) for any other device type.
+ */
+uint32_t pcie_device_port_type(uint32_t bdf)
+{
+	uint32_t pciecs_base, reg_value, dp_type;
+
+	/*
+	 * Get the PCI Express Capability structure offset and
+	 * use that offset to read pci express capabilities register
+	 */
+	pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &pciecs_base);
+	reg_value = pcie_read_cfg(bdf, pciecs_base + CIDR_OFFSET);
+
+	/* Read Device/Port bits [7:4] in Function's PCIe Capabilities register */
+	dp_type = (reg_value >> ((PCIECR_OFFSET - CIDR_OFFSET)*8 +
+				PCIECR_DPT_SHIFT)) & PCIECR_DPT_MASK;
+	dp_type = (1 << dp_type);
+
+	/* Check if the device/port is an on-chip peripheral */
+	if (pcie_is_onchip_peripheral(bdf)) {
+		if (dp_type == EP) {
+			dp_type = iEP_EP;
+		} else if (dp_type == RP) {
+			dp_type = iEP_RP;
+		}
+	}
+
+	/* Return device/port type */
+	return dp_type;
+}
+
+/*
+ * @brief  Returns BDF of the upstream Root Port of a pcie device function.
+ *
+ * @param  bdf	     - Function's Segment/Bus/Dev/Func in PCIE_CREATE_BDF format
+ * @param  usrp_bdf  - Upstream Rootport bdf in PCIE_CREATE_BDF format
+ * @return 0 for success, 1 for failure.
+ */
+uint32_t pcie_get_rootport(uint32_t bdf, uint32_t *rp_bdf)
+{
+	uint32_t seg_num, sec_bus, sub_bus;
+	uint32_t reg_value, dp_type, index = 0;
+
+	dp_type = pcie_device_port_type(bdf);
+
+	PCIE_DEBUG("DP type 0x%x\n", dp_type);
+
+	/* If the device is RP or iEP_RP, set its rootport value to same */
+	if ((dp_type == RP) || (dp_type == iEP_RP)) {
+		*rp_bdf = bdf;
+		return 0;
+	}
+
+	/* If the device is RCiEP and RCEC, set RP as 0xff */
+	if ((dp_type == RCiEP) || (dp_type == RCEC)) {
+		*rp_bdf = 0xffffffff;
+		return 1;
+	}
+
+	while (index < g_pcie_bdf_table->num_entries) {
+		*rp_bdf = g_pcie_bdf_table->device[index++].bdf;
+
+		/*
+		 * Extract Secondary and Subordinate Bus numbers of the
+		 * upstream Root port and check if the input function's
+		 * bus number falls within that range.
+		 */
+		reg_value = pcie_read_cfg(*rp_bdf, TYPE1_PBN);
+		seg_num = PCIE_EXTRACT_BDF_SEG(*rp_bdf);
+		sec_bus = ((reg_value >> SECBN_SHIFT) & SECBN_MASK);
+		sub_bus = ((reg_value >> SUBBN_SHIFT) & SUBBN_MASK);
+		dp_type = pcie_device_port_type(*rp_bdf);
+
+		if (((dp_type == RP) || (dp_type == iEP_RP)) &&
+			(sec_bus <= PCIE_EXTRACT_BDF_BUS(bdf)) &&
+			(sub_bus >= PCIE_EXTRACT_BDF_BUS(bdf)) &&
+			(seg_num == PCIE_EXTRACT_BDF_SEG(bdf)))
+			return 0;
+		}
+
+		/* Return failure */
+		ERROR("PCIe Hierarchy fail: RP of bdf 0x%x not found\n", bdf);
+		*rp_bdf = 0;
+		return 1;
+}
+
+/*
+ * @brief  Sanity checks that all Endpoints must have a Rootport
+ *
+ * @param  None
+ * @return 0 if sanity check passes, 1 if sanity check fails
+ */
+static uint32_t pcie_populate_device_rootport(void)
+{
+	uint32_t bdf, rp_bdf;
+	pcie_device_bdf_table_t *bdf_tbl_ptr = g_pcie_bdf_table;
+
+	for (unsigned int tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries;
+								tbl_index++) {
+		bdf = bdf_tbl_ptr->device[tbl_index].bdf;
+
+		/* Checks if the BDF has RootPort */
+		pcie_get_rootport(bdf, &rp_bdf);
+
+		bdf_tbl_ptr->device[tbl_index].rp_bdf = rp_bdf;
+		PCIE_DEBUG("Dev bdf: 0x%x RP bdf: 0x%x\n", bdf, rp_bdf);
+	}
+
+	return 0;
+}
+
+/*
+ * @brief  Returns the BDF Table pointer
+ *
+ * @param  None
+ *
+ * @return BDF Table pointer
+ */
+pcie_device_bdf_table_t *pcie_get_bdf_table(void)
+{
+	return g_pcie_bdf_table;
+}
+
+/*
+ * @brief   This API creates the device bdf table from enumeration
+ *
+ * @param   None
+ *
+ * @return  None
+ */
+void pcie_create_device_bdf_table(void)
+{
+	uint32_t seg_num, start_bus, end_bus;
+	uint32_t bus_index, dev_index, func_index, ecam_index;
+	uint32_t bdf, reg_value, cid_offset, status;
+
+	assert(g_pcie_bdf_table != NULL);
+
+	g_pcie_bdf_table->num_entries = 0;
+	assert(g_pcie_info_table->num_entries != 0);
+
+	for (ecam_index = 0; ecam_index < g_pcie_info_table->num_entries; ecam_index++) {
+		/* Derive ECAM specific information */
+		const pcie_info_block_t *block = &g_pcie_info_table->block[ecam_index];
+
+		seg_num = block->segment_num;
+		start_bus = block->start_bus_num;
+		end_bus = block->end_bus_num;
+
+		/* Iterate over all buses, devices and functions in this ecam */
+		for (bus_index = start_bus; bus_index <= end_bus; bus_index++) {
+			for (dev_index = 0; dev_index < PCIE_MAX_DEV; dev_index++) {
+				for (func_index = 0; func_index < PCIE_MAX_FUNC; func_index++) {
+					/* Form BDF using seg, bus, device, function numbers */
+					bdf = PCIE_CREATE_BDF(seg_num, bus_index, dev_index,
+										func_index);
+
+					/* Probe PCIe device Function with this BDF */
+					reg_value = pcie_read_cfg(bdf, TYPE01_VIDR);
+
+					/* Store the Function's BDF if there was a valid response */
+					if (reg_value != PCIE_UNKNOWN_RESPONSE) {
+						/* Skip if the device is a host bridge */
+						if (pcie_is_host_bridge(bdf)) {
+							continue;
+						}
+
+						/* Skip if the device is a PCI legacy device */
+						if (pcie_find_capability(bdf, PCIE_CAP,
+							CID_PCIECS,  &cid_offset) != PCIE_SUCCESS) {
+							continue;
+						}
+
+						status = pcie_check_device_valid(bdf);
+						if (!status) {
+							continue;
+						}
+
+						g_pcie_bdf_table->device[
+							g_pcie_bdf_table->num_entries++].bdf = bdf;
+					}
+				}
+			}
+		}
+	}
+
+	/* Sanity Check : Confirm all EP (normal, integrated) have a rootport */
+	pcie_populate_device_rootport();
+	INFO("Number of BDFs found     : %u\n", g_pcie_bdf_table->num_entries);
+}
+
+/*
+ * @brief  Returns the header type of the input pcie device function
+ *
+ * @param  bdf   - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF
+ * @return TYPE0_HEADER for functions with Type 0 config space header,
+ *         TYPE1_HEADER for functions with Type 1 config space header,
+ */
+uint32_t pcie_function_header_type(uint32_t bdf)
+{
+	/* Read four bytes of config space starting from cache line size register */
+	uint32_t reg_value = pcie_read_cfg(bdf, TYPE01_CLSR);
+
+	/* Extract header type register value */
+	reg_value = ((reg_value >> TYPE01_HTR_SHIFT) & TYPE01_HTR_MASK);
+
+	/* Header layout bits within header type register indicate the header type */
+	return ((reg_value >> HTR_HL_SHIFT) & HTR_HL_MASK);
+}
+
+/*
+ * @brief  Returns the ECAM address of the input PCIe function
+ *
+ * @param  bdf   - Segment/Bus/Dev/Func in PCIE_CREATE_BDF format
+ * @return ECAM address if success, else NULL address
+ */
+uintptr_t pcie_get_ecam_base(uint32_t bdf)
+{
+	uint8_t ecam_index = 0, sec_bus = 0, sub_bus;
+	uint16_t seg_num = (uint16_t)PCIE_EXTRACT_BDF_SEG(bdf);
+	uint32_t reg_value;
+	uintptr_t ecam_base = 0;
+
+	while (ecam_index < g_pcie_info_table->num_entries) {
+		/* Derive ECAM specific information */
+		const pcie_info_block_t *block = &g_pcie_info_table->block[ecam_index];
+
+		if (seg_num == block->segment_num) {
+			if (pcie_function_header_type(bdf) == TYPE0_HEADER) {
+				/* Return ecam_base if Type0 Header */
+				ecam_base = block->ecam_base;
+				break;
+			}
+
+			/* Check for Secondary/Subordinate bus if Type1 Header */
+			reg_value = pcie_read_cfg(bdf, TYPE1_PBN);
+			sec_bus = ((reg_value >> SECBN_SHIFT) & SECBN_MASK);
+			sub_bus = ((reg_value >> SUBBN_SHIFT) & SUBBN_MASK);
+
+			if ((sec_bus >= block->start_bus_num) &&
+			    (sub_bus <= block->end_bus_num)) {
+				ecam_base = block->ecam_base;
+				break;
+			}
+		}
+		ecam_index++;
+	}
+
+	return ecam_base;
+}
+
+/*
+ * @brief   This API prints all the PCIe Devices info
+ * 1. Caller	   -  Validation layer.
+ * 2. Prerequisite -  val_pcie_create_info_table()
+ * @param   None
+ * @return  None
+ */
+void pcie_print_device_info(void)
+{
+	uint32_t bdf, dp_type;
+	uint32_t tbl_index = 0;
+	uint32_t ecam_index = 0;
+	uint32_t ecam_base, ecam_start_bus, ecam_end_bus;
+	pcie_device_bdf_table_t *bdf_tbl_ptr = g_pcie_bdf_table;
+	uint32_t num_rciep = 0, num_rcec = 0;
+	uint32_t num_iep = 0, num_irp = 0;
+	uint32_t num_ep = 0, num_rp = 0;
+	uint32_t num_dp = 0, num_up = 0;
+	uint32_t num_pcie_pci = 0, num_pci_pcie = 0;
+	uint32_t bdf_counter;
+
+	if (bdf_tbl_ptr->num_entries == 0) {
+		INFO("BDF Table: No RCiEP or iEP found\n");
+		return;
+	}
+
+	for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++) {
+		bdf = bdf_tbl_ptr->device[tbl_index].bdf;
+		dp_type = pcie_device_port_type(bdf);
+
+		switch (dp_type) {
+		case RCiEP:
+			num_rciep++;
+			break;
+		case RCEC:
+			num_rcec++;
+			break;
+		case EP:
+			num_ep++;
+			break;
+		case RP:
+			num_rp++;
+			break;
+		case iEP_EP:
+			num_iep++;
+			break;
+		case iEP_RP:
+			num_irp++;
+			break;
+		case UP:
+			num_up++;
+			break;
+		case DP:
+			num_dp++;
+			break;
+		case PCI_PCIE:
+			num_pci_pcie++;
+			break;
+		case PCIE_PCI:
+			num_pcie_pci++;
+			break;
+		default:
+			ERROR("Unknown dp_type 0x%x\n", dp_type);
+		}
+	}
+
+	INFO("Number of RCiEP          : %u\n", num_rciep);
+	INFO("Number of RCEC           : %u\n", num_rcec);
+	INFO("Number of EP             : %u\n", num_ep);
+	INFO("Number of RP             : %u\n", num_rp);
+	INFO("Number of iEP_EP         : %u\n", num_iep);
+	INFO("Number of iEP_RP         : %u\n", num_irp);
+	INFO("Number of UP of switch   : %u\n", num_up);
+	INFO("Number of DP of switch   : %u\n", num_dp);
+	INFO("Number of PCI/PCIe Bridge: %u\n", num_pci_pcie);
+	INFO("Number of PCIe/PCI Bridge: %u\n", num_pcie_pci);
+
+	while (ecam_index < g_pcie_info_table->num_entries) {
+
+		/* Derive ECAM specific information */
+		const pcie_info_block_t *block = &g_pcie_info_table->block[ecam_index];
+
+		ecam_base = block->ecam_base;
+		ecam_start_bus = block->start_bus_num;
+		ecam_end_bus = block->end_bus_num;
+		tbl_index = 0;
+		bdf_counter = 0;
+
+		INFO("ECAM %u: base 0x%x\n", ecam_index, ecam_base);
+
+		while (tbl_index < bdf_tbl_ptr->num_entries) {
+			uint32_t seg_num, bus_num, dev_num, func_num;
+			uint32_t device_id, vendor_id, reg_value;
+			uint32_t bdf, dev_ecam_base;
+
+			bdf = bdf_tbl_ptr->device[tbl_index++].bdf;
+			seg_num  = PCIE_EXTRACT_BDF_SEG(bdf);
+			bus_num  = PCIE_EXTRACT_BDF_BUS(bdf);
+			dev_num  = PCIE_EXTRACT_BDF_DEV(bdf);
+			func_num = PCIE_EXTRACT_BDF_FUNC(bdf);
+
+			reg_value = pcie_read_cfg(bdf, TYPE01_VIDR);
+			device_id = (reg_value >> TYPE01_DIDR_SHIFT) & TYPE01_DIDR_MASK;
+			vendor_id = (reg_value >> TYPE01_VIDR_SHIFT) & TYPE01_VIDR_MASK;
+
+			dev_ecam_base = pcie_get_ecam_base(bdf);
+
+			if ((ecam_base == dev_ecam_base) &&
+				(bus_num >= ecam_start_bus) &&
+				(bus_num <= ecam_end_bus)) {
+				bdf_counter = 1;
+				bdf = PCIE_CREATE_BDF(seg_num, bus_num, dev_num, func_num);
+				INFO("  BDF: 0x%x\n", bdf);
+				INFO("  Seg: 0x%x Bus: 0x%x Dev: 0x%x "
+					"Func: 0x%x Dev ID: 0x%x Vendor ID: 0x%x\n",
+					seg_num, bus_num, dev_num, func_num,
+					device_id, vendor_id);
+			}
+		}
+
+		if (bdf_counter == 0) {
+			INFO("  No BDF devices in ECAM region index %d\n", ecam_index);
+		}
+
+		ecam_index++;
+	}
+}
+
+/*
+ * @brief	Create PCIe table and PCI enumeration
+ * @param	void
+ * @return	void
+ */
+void pcie_create_info_table(void)
+{
+	unsigned int num_ecam;
+
+	INFO("Creating PCIe info table\n");
+
+	g_pcie_info_table = plat_pcie_get_info_table();
+	g_pcie_bdf_table = pcie_bdf_table;
+
+	num_ecam = g_pcie_info_table->num_entries;
+	INFO("Number of ECAM regions   : %u\n", num_ecam);
+	if (num_ecam == 0) {
+		return;
+	}
+	pcie_create_device_bdf_table();
+	pcie_print_device_info();
+}
diff --git a/lib/pcie/pcie_doe.c b/lib/pcie/pcie_doe.c
new file mode 100644
index 0000000..7cdbd66
--- /dev/null
+++ b/lib/pcie/pcie_doe.c
@@ -0,0 +1,226 @@
+/*
+ * Copyright (c) 2024, Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdlib.h>
+#include <debug.h>
+#include <errno.h>
+#include <string.h>
+#include <pcie.h>
+#include <pcie_doe.h>
+#include <tftf_lib.h>
+
+#if LOG_LEVEL >= LOG_LEVEL_INFO
+#define DOE_INFO(...)	mp_printf(__VA_ARGS__)
+#else
+#define DOE_INFO(...)
+#endif
+
+static int pcie_doe_wait_ready(uint32_t bdf, uint32_t doe_cap_base)
+{
+	uint32_t value;
+
+	for (unsigned int i = 0; i < PCI_DOE_POLL_LOOP; i++) {
+		value = pcie_read_cfg(bdf, doe_cap_base + DOE_STATUS_REG);
+
+		if ((value & DOE_STATUS_BUSY_BIT) != 0) {
+			ERROR("DOE Busy bit is set\n");
+			return -EBUSY;
+		}
+
+		if ((value & DOE_STATUS_ERROR_BIT) != 0) {
+			ERROR("DOE Error bit is set\n");
+			return -EIO;
+		}
+
+		if ((value & DOE_STATUS_READY_BIT) != 0) {
+			return 0;
+		}
+
+		waitms(PCI_DOE_POLL_TIME);
+	}
+
+	ERROR("DOE Timeout, status 0x%x\n", value);
+	return -ETIMEDOUT;
+}
+
+static const char * const doe_object_type[] = {
+	"DOE Discovery",
+	"CMA-SPDM",
+	"Secured CMA-SPDM",
+	/* PCI Express Base Specification Revision 6.1 */
+	"CMA/SPDM with Connection ID",
+	"Secured CMA/SPDM with Connection ID",
+	"Async Message"
+};
+
+void print_doe_disc(pcie_doe_disc_resp_t *data)
+{
+	uint8_t type = data->data_object_type;
+
+	INFO("Vendor ID: 0x%x, ", data->vendor_id);
+
+	if (type >= ARRAY_SIZE(doe_object_type)) {
+		DOE_INFO("Unknown type: 0x%x\n", type);
+	} else {
+		DOE_INFO("%s\n", doe_object_type[type]);
+	}
+}
+
+static void print_doe_data(uint32_t idx, uint32_t data, bool last)
+{
+	uint32_t j = idx + DOE_HEADER_LENGTH;
+
+	if (last) {
+		if ((j & 7) == 0) {
+			INFO(" %08x\n", data);
+		} else {
+			DOE_INFO(" %08x\n", data);
+		}
+	} else if ((j & 7) == 0) {
+		INFO(" %08x", data);
+	} else if ((j & 7) == 7) {
+		DOE_INFO(" %08x\n", data);
+	} else {
+		DOE_INFO(" %08x", data);
+	}
+}
+
+/*
+ * @brief   This API sends DOE request to PCI device.
+ * @param   bdf - concatenated Bus(8-bits), device(8-bits) & function(8-bits)
+ * @param   doe_cap_base - DOE capability base offset
+ * @param   *req_addr - DOE request payload buffer
+ * @param   req_len - DOE request payload length in bytes
+ *
+ * @return  0 on success, negative code on failure
+ */
+int pcie_doe_send_req(uint32_t header, uint32_t bdf, uint32_t doe_cap_base,
+			uint32_t *req_addr, uint32_t req_len)
+{
+	uint32_t value, i, send_length, rem_length, doe_length;
+
+	value = pcie_read_cfg(bdf, doe_cap_base + DOE_STATUS_REG);
+	if ((value & DOE_STATUS_BUSY_BIT) != 0) {
+		ERROR("DOE Busy bit is set\n");
+		return -EBUSY;
+	}
+
+	if ((value & DOE_STATUS_ERROR_BIT) != 0) {
+		ERROR("DOE Error bit is set\n");
+		return -EIO;
+	}
+
+	send_length = req_len >> 2;
+	rem_length = req_len & 3;
+
+	/* Calculated adjusted data length in DW */
+	doe_length = (rem_length == 0) ? send_length : (send_length + 1);
+
+	INFO(">%08x", header);
+
+	pcie_write_cfg(bdf, doe_cap_base + DOE_WRITE_DATA_MAILBOX_REG,
+								header);
+	DOE_INFO(" %08x", doe_length + DOE_HEADER_LENGTH);
+
+	pcie_write_cfg(bdf, doe_cap_base + DOE_WRITE_DATA_MAILBOX_REG,
+				doe_length + DOE_HEADER_LENGTH);
+	/* Write data */
+	for (i = 0; i < send_length; i++) {
+		print_doe_data(i, req_addr[i], false);
+		pcie_write_cfg(bdf, doe_cap_base + DOE_WRITE_DATA_MAILBOX_REG,
+								req_addr[i]);
+	}
+
+	/* Check for remaining bytes */
+	if (rem_length != 0) {
+		value = 0;
+		(void)memcpy(&value, &req_addr[i], rem_length);
+		print_doe_data(i, value, true);
+		pcie_write_cfg(bdf, doe_cap_base + DOE_WRITE_DATA_MAILBOX_REG, value);
+
+	} else if (((i + DOE_HEADER_LENGTH) & 7) != 0) {
+		DOE_INFO("\n");
+	}
+
+	/* Set Go bit */
+	pcie_write_cfg(bdf, doe_cap_base + DOE_CTRL_REG, DOE_CTRL_GO_BIT);
+	return 0;
+}
+
+/*
+ * @brief   This API receives DOE response from PCI device.
+ * @param   bdf    - concatenated Bus(8-bits), device(8-bits) & function(8-bits)
+ * @param   doe_cap_base - DOE capability base offset
+ * @param   *resp_addr - DOE response payload buffer
+ * @param   *resp_len - DOE response payload length in bytes
+ *
+ * @return  0 on success, negative code on failure
+ */
+int pcie_doe_recv_resp(uint32_t bdf, uint32_t doe_cap_base,
+			uint32_t *resp_addr, uint32_t *resp_len)
+{
+	uint32_t i, value, length;
+	int ret;
+
+	/* Wait for Ready bit */
+	ret = pcie_doe_wait_ready(bdf, doe_cap_base);
+	if (ret != 0) {
+		return ret;
+	}
+
+	/*
+	 * Reading DOE Header 1:
+	 * Vendor ID and Data Object Type
+	 */
+	value = pcie_read_cfg(bdf, doe_cap_base + DOE_READ_DATA_MAILBOX_REG);
+	INFO("<%08x", value);
+
+	/* Indicate a successful transfer of the current data object DW */
+	pcie_write_cfg(bdf, doe_cap_base + DOE_READ_DATA_MAILBOX_REG, 0);
+
+	/*
+	 * Reading DOE Header 2:
+	 * Length in DW
+	 */
+	value = pcie_read_cfg(bdf, doe_cap_base + DOE_READ_DATA_MAILBOX_REG);
+	DOE_INFO(" %08x", value);
+
+	pcie_write_cfg(bdf, doe_cap_base + DOE_READ_DATA_MAILBOX_REG, 0);
+
+	/* Check value */
+	if ((value & PCI_DOE_RESERVED_MASK) != 0) {
+		DOE_INFO("\n");
+		ERROR("DOE Data Object Header 2 error\n");
+		return -EIO;
+	}
+
+	/* Value of 00000h indicates 2^18 DW */
+	length = (value != 0) ? (value - DOE_HEADER_LENGTH) :
+				(PCI_DOE_MAX_LENGTH - DOE_HEADER_LENGTH);
+
+	/* Response payload length in bytes */
+	*resp_len = length << 2;
+
+	for (i = 0; i < length; i++) {
+		value = pcie_read_cfg(bdf, doe_cap_base + DOE_READ_DATA_MAILBOX_REG);
+		*resp_addr++ = value;
+		print_doe_data(i, value, false);
+		pcie_write_cfg(bdf, doe_cap_base + DOE_READ_DATA_MAILBOX_REG, 0);
+	}
+
+	if (((i + DOE_HEADER_LENGTH) & 7) != 0) {
+		DOE_INFO("\n");
+	}
+
+	value = pcie_read_cfg(bdf, doe_cap_base + DOE_STATUS_REG);
+	if ((value & (DOE_STATUS_READY_BIT | DOE_STATUS_ERROR_BIT)) != 0) {
+		ERROR("DOE Receive error, status 0x%x\n", value);
+		return -EIO;
+	}
+
+	return 0;
+}