feat(sme): update sme/mortlach tests
FEAT_SME is an optional architectural extension from v9.2.
Previously due to the lack of support in toolchain, testing
SME instructions were overlooked and minimal tests were added.
This patch addresses them, with additional tests to test
the SME instructions. In order to avoid toolchain requirements
we manually encode the instructions for accessing ZA array.
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ia9edd2711d548757b96495498bf9d47b9db68a09
diff --git a/lib/extensions/sme/aarch64/sme_helpers.S b/lib/extensions/sme/aarch64/sme_helpers.S
index 6261c90..c440f09 100644
--- a/lib/extensions/sme/aarch64/sme_helpers.S
+++ b/lib/extensions/sme/aarch64/sme_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,11 +8,52 @@
#include <asm_macros.S>
#include <assert_macros.S>
-#ifdef __aarch64__
-
.arch armv8-a+sve
.globl sme_rdvl_1
.globl sme_try_illegal_instruction
+ .globl sme_vector_to_ZA
+ .globl sme_ZA_to_vector
+
+
+/*
+ * TODO: Due to the limitation with toolchain, SME intrinsics, still not being
+ * supported, instructions are manually encoded using the opcodes.
+ * Further, when the toolchain supports the requirements, these macros could
+ * be refactored.
+ */
+
+
+/*
+ * LDR (Loads a vector (an array of elements ) to ZA array ):
+ * LDR ZA[\nw, #\offset], [X\nxbase, #\offset, MUL VL]
+ *
+ * Arguments/Opcode bit field:
+ * nw : the vector select register W12-W15
+ * nxbase : 64-bit name of the general-purpose base register.
+ * offset : vector select and optional memory offset. Default to 0.
+ */
+.macro _ldr_za nw, nxbase, offset=0
+ .inst 0xe1000000 \
+ | (((\nw) & 3) << 13) \
+ | ((\nxbase) << 5) \
+ | ((\offset) & 0xf)
+.endm
+
+/*
+ * STR ( It stores an array of elements from ZA array to a vector ).
+ * STR ZA[\nw, #\offset], [X\nxbase, #\offset, MUL VL]
+ *
+ * Arguments/Opcode bit field:
+ * nw : the vector select register W12-W15
+ * nxbase : 64-bit name of the general-purpose base register.
+ * offset : vector select and optional memory offset. Default to 0.
+ */
+.macro _str_za nw, nxbase, offset=0
+ .inst 0xe1200000 \
+ | (((\nw) & 3) << 13) \
+ | ((\nxbase) << 5) \
+ | ((\offset) & 0xf)
+.endm
/*
* uint64_t sme_rdvl_1(void);
@@ -36,4 +77,25 @@
ret
endfunc sme_try_illegal_instruction
-#endif /* __aarch64__ */
+
+/**
+ * void sme_vector_to_ZA(uint64_t *input_vec)
+ *
+ * This function loads an vector of elements to an ZA Array storage
+ */
+func sme_vector_to_ZA
+ mov w12, wzr
+ _ldr_za 12, 0 // ZA.H[W12] loaded from [X0 / input_vector]
+ ret
+endfunc sme_vector_to_ZA
+
+/**
+ * void sme_ZA_to_vector(uint64_t *out_vec)
+ *
+ * This function stores elements from ZA Array storage to an ZA vector
+ */
+func sme_ZA_to_vector
+ mov w12, wzr
+ _str_za 12, 0 // ZA.H[W12] stored to [X0 / out_vector]
+ ret
+endfunc sme_ZA_to_vector