diff --git a/tftf/tests/extensions/ls64/ls64_operations.S b/tftf/tests/extensions/ls64/ls64_operations.S
new file mode 100644
index 0000000..18f7a5f
--- /dev/null
+++ b/tftf/tests/extensions/ls64/ls64_operations.S
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+
+#if __aarch64__
+
+        .arch armv8.7-a
+	.globl	ls64_store
+	.globl	ls64_load
+
+/*
+ * Function to store 64 bytes of data from consecutive registers into a memory
+ * location in single-copy atomic operation via st64b instruction.
+ *
+ * x0:     Holds the base address of the input array of 8 64-bit integers.
+ * x1:     Holds the base address of the destination/output array of 8 64-bit
+ *         integers, where st64b does the single-copy atomic 64-byte store.
+ * x8-x15: Consecutive registers loaded with input array.
+ *
+ */
+func ls64_store
+	ldp	x8, x9, [x0, #0]	/* x0: Base address of Input Array */
+	ldp	x10, x11, [x0, #16]
+	ldp	x12, x13, [x0, #32]
+	ldp	x14, x15, [x0, #48]
+	st64b	x8, [x1]		/* x1: Address where 64-byte data to be stored */
+	ret
+endfunc ls64_store
+
+/*
+ * Function to load 64-byte of data from a memory location to eight consecutive
+ *  64-bit registers in single-copy atomic operation via ld64b instruction.
+ *
+ * x0: Holds the address of memory from where 64-byte of data to be loaded.
+ * x1: Holds the base address of the destination/output array of 8 64-bit integers.
+ * x9-x16: consecutive registers into which data will be copied with ld64b inst.
+ */
+
+func ls64_load
+	ld64b	x4, [x0]
+	stp	x4, x5, [x1, #0]	/* Base address of destination buffer */
+	stp	x6, x7, [x1, #16]
+	stp	x8, x9, [x1, #32]
+	stp	x10, x11, [x1, #48]
+	ret
+endfunc ls64_load
+
+#endif /* __aarch64__ */
diff --git a/tftf/tests/extensions/ls64/test_ls64.c b/tftf/tests/extensions/ls64/test_ls64.c
new file mode 100644
index 0000000..b7074ab
--- /dev/null
+++ b/tftf/tests/extensions/ls64/test_ls64.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "./test_ls64.h"
+#include <test_helpers.h>
+
+/*
+ * @brief Test LS64 feature support when the extension is enabled.
+ *
+ * Execute the LS64 instructions:
+ * LD64B   -  single-copy atomic 64-byte load.
+ * ST64B   -  single-copy atomic 64-byte store without return.
+ *
+ * These instructions should not be trapped to EL3, when EL2 access them.
+ *
+ * @return test_result_t
+ */
+test_result_t test_ls64_instructions(void)
+{
+#if PLAT_fvp
+#ifdef __aarch64__
+
+	/* Make sure FEAT_LS64 is supported. */
+	SKIP_TEST_IF_LS64_NOT_SUPPORTED();
+
+	uint64_t ls64_input_buffer[LS64_ARRAYSIZE] = {1, 2, 3, 4, 5, 6, 7, 8};
+	uint64_t ls64_output_buffer[LS64_ARRAYSIZE] = {0};
+	/*
+	 * Address where the data will be written to/read from with instructions
+	 * st64b and ld64b respectively.
+	 * Can only be in range (0x1d000000 - 0x1d00ffff) and be 64-byte aligned.
+	 */
+	uint64_t *store_address = (uint64_t *)LS64_ATOMIC_DEVICE_BASE;
+
+	/**
+	 * FEAT_LS64 : Execute LD64B and ST64B Instructions.
+	 * This test copies data from input buffer, an array of 8-64bit
+	 * unsigned integers to an output buffer via LD64B and ST64B
+	 * atomic operation instructions.
+	 *
+	 * NOTE: As we cannot pre-write into LS64_ATOMIC_DEVICE_BASE memory
+	 * via other instructions, we first load the data from a normal
+	 * input buffer into the consecutive registers and then copy them in one
+	 * atomic operation via st64b to Device memory(LS64_ATOMIC_DEVICE_BASE).
+	 * Further we load the data from the same device memory into a normal
+	 * output buffer through general registers and verify the buffers to
+	 * ensure instructions copied the data as per the architecture.
+	 */
+
+	ls64_store(ls64_input_buffer, store_address);
+	ls64_load(store_address, ls64_output_buffer);
+
+	for (uint8_t i = 0U; i < LS64_ARRAYSIZE; i++) {
+		VERBOSE("Input Buffer[%lld]=%lld\n", i, ls64_input_buffer[i]);
+		VERBOSE("Output Buffer[%lld]=%lld\n", i, ls64_output_buffer[i]);
+
+		if (ls64_input_buffer[i] != ls64_output_buffer[i]) {
+			return TEST_RESULT_FAIL;
+		}
+	}
+
+	return TEST_RESULT_SUCCESS;
+#else
+	/* Skip test if AArch32 */
+	SKIP_TEST_IF_AARCH32();
+#endif /* __aarch64_ */
+#else
+	tftf_testcase_printf("Test supported only on FVP \n");
+	return TEST_RESULT_SKIPPED;
+#endif /* PLAT_fvp */
+
+}
diff --git a/tftf/tests/extensions/ls64/test_ls64.h b/tftf/tests/extensions/ls64/test_ls64.h
new file mode 100644
index 0000000..35a00c2
--- /dev/null
+++ b/tftf/tests/extensions/ls64/test_ls64.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TEST_LS64_H
+#define TEST_LS64_H
+
+#include <stdint.h>
+
+#define LS64_ARRAYSIZE 8
+
+void ls64_store(uint64_t *input_buffer, uint64_t *store_address);
+void ls64_load(uint64_t *store_address, uint64_t *output_buffer);
+
+#endif /* TEST_LS64_H */
diff --git a/tftf/tests/tests-cpu-extensions.mk b/tftf/tests/tests-cpu-extensions.mk
index 51f2e55..144694e 100644
--- a/tftf/tests/tests-cpu-extensions.mk
+++ b/tftf/tests/tests-cpu-extensions.mk
@@ -11,10 +11,12 @@
 	extensions/debugv8p9/test_debugv8p9.c				\
 	extensions/ecv/test_ecv.c					\
 	extensions/fgt/test_fgt.c					\
-	extensions/pmuv3/test_pmuv3.c					\
+	extensions/ls64/test_ls64.c 					\
+	extensions/ls64/ls64_operations.S				\
 	extensions/mpam/test_mpam.c					\
 	extensions/mte/test_mte.c					\
 	extensions/pauth/test_pauth.c					\
+	extensions/pmuv3/test_pmuv3.c					\
 	extensions/sme/test_sme.c					\
 	extensions/sme/test_sme2.c					\
 	extensions/spe/test_spe.c					\
diff --git a/tftf/tests/tests-cpu-extensions.xml b/tftf/tests/tests-cpu-extensions.xml
index 0f8d0f6..22ae510 100644
--- a/tftf/tests/tests-cpu-extensions.xml
+++ b/tftf/tests/tests-cpu-extensions.xml
@@ -35,6 +35,7 @@
     <testcase name="PMUv3 cycle counter functional in NS" function="test_pmuv3_cycle_works_ns" />
     <testcase name="PMUv3 event counter functional in NS" function="test_pmuv3_event_works_ns" />
     <testcase name="PMUv3 SMC counter preservation" function="test_pmuv3_el3_preserves" />
+    <testcase name="LS64 support" function="test_ls64_instructions" />
   </testsuite>
 
   <testsuite name="ARM_ARCH_SVC" description="Arm Architecture Service tests">