ld: Separate code and RO data sections
This prevents the execution of the read-only data.
This is done in a similar way in TF-A when the build flag
SEPARATE_CODE_AND_RODATA is enabled.
The build flag is probably not needed in TF-A Tests.
Change-Id: I2bdc0237c00377beb2febeb47207770c85036192
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
diff --git a/fwu/ns_bl1u/ns_bl1u.ld.S b/fwu/ns_bl1u/ns_bl1u.ld.S
index 2ca5292..52d80de 100644
--- a/fwu/ns_bl1u/ns_bl1u.ld.S
+++ b/fwu/ns_bl1u/ns_bl1u.ld.S
@@ -12,22 +12,29 @@
ENTRY(ns_bl1u_entrypoint)
MEMORY {
- ROM (rx): ORIGIN = NS_BL1U_RO_BASE, LENGTH = NS_BL1U_RO_LIMIT - NS_BL1U_RO_BASE
+ ROM (rx): ORIGIN = NS_BL1U_BASE, LENGTH = NS_BL1U_RO_LIMIT - NS_BL1U_BASE
RAM (rwx): ORIGIN = NS_BL1U_RW_BASE, LENGTH = NS_BL1U_RW_LIMIT - NS_BL1U_RW_BASE
}
SECTIONS
{
- . = NS_BL1U_RO_BASE;
+ . = NS_BL1U_BASE;
ASSERT(. == ALIGN(PAGE_SIZE),
- "NS_BL1U_RO_BASE address is not aligned on a page boundary.")
+ "NS_BL1U_BASE address is not aligned on a page boundary.")
- ro . : {
- __RO_START__ = .;
+ .text . : {
+ __TEXT_START__ = .;
*ns_bl1u_entrypoint.o(.text*)
*(.text*)
+ . = ALIGN(PAGE_SIZE);
+ __TEXT_END__ = .;
+ } >ROM
+
+ .rodata . : {
+ __RODATA_START__ = .;
*(.rodata*)
- __RO_END__ = .;
+ . = ALIGN(PAGE_SIZE);
+ __RODATA_END__ = .;
} >ROM
/*
diff --git a/fwu/ns_bl2u/ns_bl2u.ld.S b/fwu/ns_bl2u/ns_bl2u.ld.S
index 48af303..a6c6d2e 100644
--- a/fwu/ns_bl2u/ns_bl2u.ld.S
+++ b/fwu/ns_bl2u/ns_bl2u.ld.S
@@ -21,20 +21,25 @@
ASSERT(. == ALIGN(PAGE_SIZE),
"NS_BL2U_BASE address is not aligned on a page boundary.")
- ro . : {
- __RO_START__ = .;
+ .text . : {
+ __TEXT_START__ = .;
*ns_bl2u_entrypoint.o(.text*)
*(.text*)
- *(.rodata*)
*(.vectors)
- __RO_END_UNALIGNED__ = .;
+ . = ALIGN(PAGE_SIZE);
+ __TEXT_END__ = .;
+ } >RAM
+
+ .rodata . : {
+ __RODATA_START__ = .;
+ *(.rodata*)
/*
* Memory page(s) mapped to this section will be marked as
- * read-only, executable. No RW data from the next section must
+ * read-only, non-executable. No RW data from the next section must
* creep in. Ensure the rest of the current memory page is unused.
*/
. = ALIGN(PAGE_SIZE);
- __RO_END__ = .;
+ __RODATA_END__ = .;
} >RAM
.data . : {
diff --git a/plat/arm/fvp/include/platform_def.h b/plat/arm/fvp/include/platform_def.h
index 31b012a..4f64079 100644
--- a/plat/arm/fvp/include/platform_def.h
+++ b/plat/arm/fvp/include/platform_def.h
@@ -70,8 +70,8 @@
* NS_BL1U RW data is relocated from NS-ROM to NS-RAM at runtime so we
* need 2 sets of addresses.
******************************************************************************/
-#define NS_BL1U_RO_BASE (0x08000000 + 0x03EB8000)
-#define NS_BL1U_RO_LIMIT (NS_BL1U_RO_BASE + 0xC000)
+#define NS_BL1U_BASE (0x08000000 + 0x03EB8000)
+#define NS_BL1U_RO_LIMIT (NS_BL1U_BASE + 0xC000)
/*******************************************************************************
* Put NS_BL1U RW at the top of the Non-Trusted SRAM. NS_BL1U_RW_BASE is
diff --git a/plat/arm/juno/include/platform_def.h b/plat/arm/juno/include/platform_def.h
index 682866c..4be8645 100644
--- a/plat/arm/juno/include/platform_def.h
+++ b/plat/arm/juno/include/platform_def.h
@@ -81,8 +81,8 @@
* NS_BL1U RW data is relocated from NS-ROM to NS-RAM at runtime so we
* need 2 sets of addresses.
******************************************************************************/
-#define NS_BL1U_RO_BASE (0x08000000 + 0x03EB8000)
-#define NS_BL1U_RO_LIMIT (NS_BL1U_RO_BASE + 0xC000)
+#define NS_BL1U_BASE (0x08000000 + 0x03EB8000)
+#define NS_BL1U_RO_LIMIT (NS_BL1U_BASE + 0xC000)
/*******************************************************************************
* Put NS_BL1U RW at the top of the Non-Trusted SRAM. NS_BL1U_RW_BASE is
diff --git a/plat/common/plat_common.c b/plat/common/plat_common.c
index c5f4592..4cfbebb 100644
--- a/plat/common/plat_common.c
+++ b/plat/common/plat_common.c
@@ -27,32 +27,40 @@
#if IMAGE_TFTF
-#define IMAGE_RO_BASE TFTF_BASE
-IMPORT_SYM(uintptr_t, __RO_END__, IMAGE_RO_END);
+#define IMAGE_TEXT_BASE TFTF_BASE
+IMPORT_SYM(uintptr_t, __TEXT_END__, IMAGE_TEXT_END);
-#define IMAGE_RW_BASE IMAGE_RO_END
-IMPORT_SYM(uintptr_t, __TFTF_END__, IMAGE_RW_END);
+#define IMAGE_RODATA_BASE IMAGE_TEXT_END
+IMPORT_SYM(uintptr_t, __RODATA_END__, IMAGE_RODATA_END);
-IMPORT_SYM(uintptr_t, __COHERENT_RAM_START__, COHERENT_RAM_START);
-IMPORT_SYM(uintptr_t, __COHERENT_RAM_END__, COHERENT_RAM_END);
+#define IMAGE_RW_BASE IMAGE_RODATA_END
+IMPORT_SYM(uintptr_t, __TFTF_END__, IMAGE_RW_END);
+
+IMPORT_SYM(uintptr_t, __COHERENT_RAM_START__, COHERENT_RAM_START);
+IMPORT_SYM(uintptr_t, __COHERENT_RAM_END__, COHERENT_RAM_END);
#elif IMAGE_NS_BL1U
-IMPORT_SYM(uintptr_t, __RO_END__, IMAGE_RO_END_UNALIGNED);
-#define IMAGE_RO_BASE NS_BL1U_RO_BASE
-#define IMAGE_RO_END round_up(IMAGE_RO_END_UNALIGNED, PAGE_SIZE)
+#define IMAGE_TEXT_BASE NS_BL1U_BASE
+IMPORT_SYM(uintptr_t, __TEXT_END__, IMAGE_TEXT_END);
-#define IMAGE_RW_BASE NS_BL1U_RW_BASE
-IMPORT_SYM(uintptr_t, __NS_BL1U_RAM_END__, IMAGE_RW_END);
+#define IMAGE_RODATA_BASE IMAGE_TEXT_END
+IMPORT_SYM(uintptr_t, __RODATA_END__, IMAGE_RODATA_END);
+
+#define IMAGE_RW_BASE NS_BL1U_RW_BASE
+IMPORT_SYM(uintptr_t, __NS_BL1U_RAM_END__, IMAGE_RW_END);
#elif IMAGE_NS_BL2U
-#define IMAGE_RO_BASE NS_BL2U_BASE
-IMPORT_SYM(uintptr_t, __RO_END__, IMAGE_RO_END);
+#define IMAGE_TEXT_BASE NS_BL2U_BASE
+IMPORT_SYM(uintptr_t, __TEXT_END__, IMAGE_TEXT_END);
-#define IMAGE_RW_BASE IMAGE_RO_END
-IMPORT_SYM(uintptr_t, __NS_BL2U_END__, IMAGE_RW_END_UNALIGNED);
-#define IMAGE_RW_END round_up(IMAGE_RW_END_UNALIGNED, PAGE_SIZE)
+#define IMAGE_RODATA_BASE IMAGE_TEXT_END
+IMPORT_SYM(uintptr_t, __RODATA_END__, IMAGE_RODATA_END);
+
+#define IMAGE_RW_BASE IMAGE_RODATA_END
+IMPORT_SYM(uintptr_t, __NS_BL2U_END__, IMAGE_RW_END_UNALIGNED);
+#define IMAGE_RW_END round_up(IMAGE_RW_END_UNALIGNED, PAGE_SIZE)
#endif
@@ -78,9 +86,13 @@
void tftf_plat_configure_mmu(void)
{
- /* RO data + Code */
- mmap_add_region(IMAGE_RO_BASE, IMAGE_RO_BASE,
- IMAGE_RO_END - IMAGE_RO_BASE, MT_CODE);
+ /* Code */
+ mmap_add_region(IMAGE_TEXT_BASE, IMAGE_TEXT_BASE,
+ IMAGE_TEXT_END - IMAGE_TEXT_BASE, MT_CODE);
+
+ /* RO data */
+ mmap_add_region(IMAGE_RODATA_BASE, IMAGE_RODATA_BASE,
+ IMAGE_RODATA_END - IMAGE_RODATA_BASE, MT_RO_DATA);
/* Data + BSS */
mmap_add_region(IMAGE_RW_BASE, IMAGE_RW_BASE,
diff --git a/tftf/framework/tftf.ld.S b/tftf/framework/tftf.ld.S
index 9432a74..364753f 100644
--- a/tftf/framework/tftf.ld.S
+++ b/tftf/framework/tftf.ld.S
@@ -21,20 +21,25 @@
. = TFTF_BASE;
__TFTF_BASE__ = .;
- ro . : {
- __RO_START__ = .;
+ .text . : {
+ __TEXT_START__ = .;
*entrypoint.o(.text*)
*(.text*)
- *(.rodata*)
*(.vectors)
- __RO_END_UNALIGNED__ = .;
+ . = NEXT(PAGE_SIZE);
+ __TEXT_END__ = .;
+ } >RAM
+
+ .rodata . : {
+ __RODATA_START__ = .;
+ *(.rodata*)
/*
* Memory page(s) mapped to this section will be marked as
* read-only, executable. No RW data from the next section must
* creep in. Ensure the rest of the current memory page is unused.
*/
. = NEXT(PAGE_SIZE);
- __RO_END__ = .;
+ __RODATA_END__ = .;
} >RAM
.data : {
diff --git a/tftf/tests/runtime_services/standard_service/psci/api_tests/system_suspend/test_psci_system_suspend.c b/tftf/tests/runtime_services/standard_service/psci/api_tests/system_suspend/test_psci_system_suspend.c
index afb352b..748c817 100644
--- a/tftf/tests/runtime_services/standard_service/psci/api_tests/system_suspend/test_psci_system_suspend.c
+++ b/tftf/tests/runtime_services/standard_service/psci/api_tests/system_suspend/test_psci_system_suspend.c
@@ -47,10 +47,10 @@
static sgi_data_t sgi_data;
static volatile int cpu_ref_count;
-extern unsigned long __RO_START__;
-#define TFTF_RO_START (unsigned long)(&__RO_START__)
-extern unsigned long __RO_END__;
-#define TFTF_RO_END (unsigned long)(&__RO_END__)
+extern unsigned long __TEXT_START__;
+#define TFTF_RO_START (unsigned long)(&__TEXT_START__)
+extern unsigned long __RODATA_END__;
+#define TFTF_RO_END (unsigned long)(&__RODATA_END__)
static int suspend_wakeup_handler(void *data)
{