diff --git a/Makefile b/Makefile
index d0aac05..0d14c4e 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2023, Arm Limited. All rights reserved.
+# Copyright (c) 2018-2024, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -135,7 +135,7 @@
 SECURE_PARTITIONS	:=
 
 # Only platform fvp supports cactus_mm
-ifeq (${ARCH}-${PLAT},aarch64-fvp)
+ifeq (${ARCH}-${PLAT},$(filter ${ARCH}-${PLAT},aarch64-fvp aarch64-rdv3))
 include spm/cactus_mm/cactus_mm.mk
 include realm/realm.mk
 endif
@@ -432,7 +432,7 @@
 	@exit 1
 endif
 
-ifneq (${ARCH}-${PLAT},aarch64-fvp)
+ifneq (${ARCH}-${PLAT},$(filter ${ARCH}-${PLAT},aarch64-fvp aarch64-rdv3))
 .PHONY: cactus_mm
 cactus_mm:
 	@echo "ERROR: $@ is supported only on AArch64 FVP."
@@ -440,7 +440,7 @@
 
 .PHONY: realm
 realm:
-	@echo "ERROR: $@ is supported only on AArch64 FVP."
+	@echo "ERROR: $@ is supported only on AArch64 FVP and RD-V3."
 	@exit 1
 
 endif
diff --git a/plat/arm/neoverse_rd/common/include/nrd3/nrd_css_def3.h b/plat/arm/neoverse_rd/common/include/nrd3/nrd_css_def3.h
new file mode 100644
index 0000000..fc96010
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/include/nrd3/nrd_css_def3.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file contains the CSS specific definitions for the third generation of
+ * platforms.
+ */
+
+#ifndef NRD_CSS_DEF3_H
+#define NRD_CSS_DEF3_H
+
+/*******************************************************************************
+ * CSS memory map related defines
+ ******************************************************************************/
+
+/* Sub-system Peripherals */
+#define NRD_CSS_PERIPH0_BASE		UL(0x2A400000)
+#define NRD_CSS_PERIPH0_SIZE		UL(0x0DC00000)
+
+/* Peripherals and PCIe expansion area */
+#define NRD_CSS_PERIPH1_BASE		UL(0x60000000)
+#define NRD_CSS_PERIPH1_SIZE		UL(0x20000000)
+
+/* DRAM base address and size */
+#define NRD_CSS_DRAM1_BASE		UL(0x80000000)
+#define NRD_CSS_DRAM1_SIZE		UL(0x80000000)
+
+/* AP Non-Secure UART related constants */
+#define NRD_CSS_NSEC_UART_BASE		UL(0x2A400000)
+
+/* Base address of trusted watchdog (SP805) */
+#define NRD_CSS_TWDOG_BASE		UL(0x2A480000)
+
+/* Base address of non-trusted watchdog (SP805) */
+#define NRD_CSS_WDOG_BASE		UL(0x2A440000)
+
+/* Memory mapped Generic timer interfaces */
+#define NRD_CSS_NSEC_CNT_BASE1			UL(0x2A830000)
+
+#endif /* NRD_CSS_DEF3_H */
\ No newline at end of file
diff --git a/plat/arm/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h b/plat/arm/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
new file mode 100644
index 0000000..245b3d7
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file contains the CSS-firmware specific definitions for the third
+ * generation of platforms.
+ */
+
+#ifndef NRD_CSS_FW_DEF3_H
+#define NRD_CSS_FW_DEF3_H
+
+#include "nrd_css_def3.h"
+
+/*******************************************************************************
+ * Console config
+ ******************************************************************************/
+
+#define NRD_CSS_NSEC_CLK_IN_HZ		UL(7372800)
+
+#endif /* NRD_CSS_FW_DEF3_H */
\ No newline at end of file
diff --git a/plat/arm/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h b/plat/arm/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
new file mode 100644
index 0000000..c09c45a
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the platform port definitions for the
+ * third generation of platforms.
+ */
+
+#ifndef NRD_PLAT_ARM_DEF3_H
+#define NRD_PLAT_ARM_DEF3_H
+
+#ifndef __ASSEMBLER__
+#include <lib/mmio.h>
+#endif /* __ASSEMBLER__ */
+
+#include <lib/utils_def.h>
+#include "nrd_css_fw_def3.h"
+#include "nrd_ros_def3.h"
+
+/* Platform binary types for linking */
+#define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH		aarch64
+
+/*******************************************************************************
+ * Stack size
+ ******************************************************************************/
+
+/* Size of cacheable stacks */
+#define PLATFORM_STACK_SIZE		U(0x1400) /* 5120 bytes */
+
+/* Size of coherent stacks */
+#define PCPU_DV_MEM_STACK_SIZE		U(0x600) /* 1536 bytes */
+
+/*******************************************************************************
+ * Core count
+ ******************************************************************************/
+
+#define PLATFORM_CORE_COUNT		(PLAT_ARM_CLUSTER_COUNT * \
+						NRD_MAX_CPUS_PER_CLUSTER)
+#define PLATFORM_NUM_AFFS		(PLAT_ARM_CLUSTER_COUNT + PLATFORM_CORE_COUNT)
+
+/*******************************************************************************
+ * Power related definitions
+ ******************************************************************************/
+
+#define PLATFORM_MAX_AFFLVL		MPIDR_AFFLVL1
+
+#define PLAT_MAX_PWR_LEVEL		PLATFORM_MAX_AFFLVL
+#define PLAT_MAX_PWR_STATES_PER_LVL	U(2)
+
+/* Local state bit width for each level in the state-ID field of power state */
+#define PLAT_LOCAL_PSTATE_WIDTH		U(4)
+
+/*******************************************************************************
+ * XLAT definitions
+ ******************************************************************************/
+
+/* Platform specific page table and MMU setup constants */
+#define MAX_XLAT_TABLES			U(7)
+#define MAX_MMAP_REGIONS		U(16)
+
+/*******************************************************************************
+ * I/O definitions
+ ******************************************************************************/
+
+/* I/O Storage NOR flash device */
+#define MAX_IO_DEVICES			U(1)
+#define MAX_IO_HANDLES			U(1)
+
+/*******************************************************************************
+ * Non-Secure Software Generated Interupts IDs
+ ******************************************************************************/
+
+/* Non-Secure Software Generated Interupts IDs */
+#define IRQ_NS_SGI_0			U(0)
+#define IRQ_NS_SGI_7			U(7)
+
+/* Maximum SPI */
+#define PLAT_MAX_SPI_OFFSET_ID		U(256)
+
+/*******************************************************************************
+ * Timer config
+ ******************************************************************************/
+
+/* Per-CPU Hypervisor Timer Interrupt ID */
+#define IRQ_PCPU_HP_TIMER		U(26)
+
+/* Memory mapped Generic timer interfaces */
+#define SYS_CNT_BASE1			NRD_CSS_NSEC_CNT_BASE1
+
+/* AP_REFCLK Generic Timer, Non-secure. */
+#define IRQ_CNTPSIRQ1			U(109)
+
+/* Times(in ms) used by test code for completion of different events */
+#define PLAT_SUSPEND_ENTRY_TIME		U(15)
+#define PLAT_SUSPEND_ENTRY_EXIT_TIME	U(30)
+
+/*******************************************************************************
+ * Console config
+ ******************************************************************************/
+
+#define PLAT_ARM_UART_BASE		NRD_CSS_NSEC_UART_BASE
+#define PLAT_ARM_UART_CLK_IN_HZ		NRD_CSS_NSEC_CLK_IN_HZ
+
+/*******************************************************************************
+ * DRAM config
+ ******************************************************************************/
+
+/* TF-A reserves DRAM space 0xFF000000- 0xFFFFFFFF for TZC */
+#define DRAM_BASE			NRD_CSS_DRAM1_BASE
+#define DRAM_SIZE			(NRD_CSS_DRAM1_SIZE - 0x1000000UL)
+
+/*******************************************************************************
+ * Cache related config
+ ******************************************************************************/
+#define CACHE_WRITEBACK_SHIFT		U(6)
+#define CACHE_WRITEBACK_GRANULE		(1U << CACHE_WRITEBACK_SHIFT)
+
+/*******************************************************************************
+ * Run-time address of the TFTF image.
+ * It has to match the location where the Trusted Firmware-A loads the BL33
+ * image.
+ ******************************************************************************/
+#define TFTF_BASE			UL(0xE0000000)
+
+/*******************************************************************************
+ * TFTF NVM configs
+ ******************************************************************************/
+
+#define TFTF_NVM_OFFSET			U(0x0)
+#define TFTF_NVM_SIZE			UL(0x08000000)	/* 128 MB */
+
+/*******************************************************************************
+ * Watchdog related config
+ ******************************************************************************/
+
+/* Base address of trusted watchdog (SP805) */
+#define SP805_TWDOG_BASE		NRD_CSS_TWDOG_BASE
+
+/* Base address of non-trusted watchdog (SP805) */
+#define SP805_WDOG_BASE		NRD_CSS_WDOG_BASE
+
+/* Trusted watchdog (SP805) Interrupt ID */
+#define IRQ_TWDOG_INTID			U(107)
+
+/*******************************************************************************
+ * Flash related config
+ ******************************************************************************/
+
+/* Base address and size of external NVM flash */
+#define FLASH_BASE			NRD_ROS_FLASH_BASE
+#define FLASH_SIZE			NRD_ROS_FLASH_SIZE
+#define NOR_FLASH_BLOCK_SIZE		UL(0x40000)     /* 256KB */
+
+#endif /* NRD_PLAT_ARM_DEF3_H */
\ No newline at end of file
diff --git a/plat/arm/neoverse_rd/common/include/nrd3/nrd_ros_def3.h b/plat/arm/neoverse_rd/common/include/nrd3/nrd_ros_def3.h
new file mode 100644
index 0000000..2822ed9
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/include/nrd3/nrd_ros_def3.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file contains the RoS specific definitions for the third generation of
+ * platforms.
+ */
+
+#ifndef NRD_ROS_DEF3_H
+#define NRD_ROS_DEF3_H
+
+/*******************************************************************************
+ * ROS configs
+ ******************************************************************************/
+
+/* Base address and size of external NVM flash */
+#define NRD_ROS_FLASH_BASE			UL(0x08000000)  /* 128MB */
+#define NRD_ROS_FLASH_SIZE			UL(0x04000000)  /* 64MB */
+
+#endif /* NRD_ROS_DEF3_H */
\ No newline at end of file
diff --git a/plat/arm/neoverse_rd/platform/rdv3/include/platform_def.h b/plat/arm/neoverse_rd/platform/rdv3/include/platform_def.h
new file mode 100644
index 0000000..f3ae5ef
--- /dev/null
+++ b/plat/arm/neoverse_rd/platform/rdv3/include/platform_def.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <nrd3/nrd_plat_arm_def3.h>
+
+#define PLAT_ARM_CLUSTER_COUNT		U(16)
+#define NRD_MAX_CPUS_PER_CLUSTER	U(1)
+#define NRD_MAX_PE_PER_CPU		U(1)
+
+/* GIC-600 & interrupt handling related constants */
+#define PLAT_ARM_GICD_BASE		UL(0x30000000)
+#define PLAT_ARM_GICR_BASE		UL(0x301C0000)
+#define PLAT_ARM_GICC_BASE		UL(0x2C000000)
+
+/* Platform specific page table and MMU setup constants */
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 46)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 46)
+
+#endif /* PLATFORM_DEF_H */
\ No newline at end of file
diff --git a/plat/arm/neoverse_rd/platform/rdv3/platform.mk b/plat/arm/neoverse_rd/platform/rdv3/platform.mk
new file mode 100644
index 0000000..3fd2cd2
--- /dev/null
+++ b/plat/arm/neoverse_rd/platform/rdv3/platform.mk
@@ -0,0 +1,21 @@
+#
+# Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include plat/arm/neoverse_rd/common/nrd_common.mk
+
+PLAT_INCLUDES		+=	-Iplat/arm/neoverse_rd/platform/rdv3/include/
+
+PLAT_SOURCES		+=	plat/arm/neoverse_rd/platform/rdv3/topology.c
+
+PLAT_TESTS_SKIP_LIST	:=	plat/arm/neoverse_rd/platform/rdv3/tests_to_skip.txt
+
+RD_V3_VARIANTS		:=	0
+
+ifneq ($(NRD_PLATFORM_VARIANT), \
+  $(filter $(NRD_PLATFORM_VARIANT),$(RD_V3_VARIANTS)))
+  $(error "NRD_PLATFORM_VARIANT for RD-V3 should be 0, currently \
+    set to ${NRD_PLATFORM_VARIANT}.")
+endif
\ No newline at end of file
diff --git a/plat/arm/neoverse_rd/platform/rdv3/tests_to_skip.txt b/plat/arm/neoverse_rd/platform/rdv3/tests_to_skip.txt
new file mode 100644
index 0000000..d5904e8
--- /dev/null
+++ b/plat/arm/neoverse_rd/platform/rdv3/tests_to_skip.txt
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# OS-initiated mode is not supported on RD-V3
+PSCI CPU Suspend in OSI mode
+
+# System suspend is not supported as there are no wakeup sources in RD-V3 FVP
+PSCI STAT/Stats test cases after system suspend
+PSCI System Suspend Validation
+
+# The following test cases result in unhandled exception at EL3
+CPU extensions/Use trace buffer control Registers
+CPU extensions/Use trace filter control Registers
+CPU extensions/Use branch record buffer control registers
+
+Framework Validation
\ No newline at end of file
diff --git a/plat/arm/neoverse_rd/platform/rdv3/topology.c b/plat/arm/neoverse_rd/platform/rdv3/topology.c
new file mode 100644
index 0000000..07e2a57
--- /dev/null
+++ b/plat/arm/neoverse_rd/platform/rdv3/topology.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <plat_topology.h>
+#include <tftf_lib.h>
+
+static const struct {
+	unsigned int cluster_id;
+	unsigned int cpu_id;
+} plat_cores[] = {
+	/* Cluster0: 1 core */
+	{ 0, 0 },
+	/* Cluster1: 1 core */
+	{ 1, 0 },
+	/* Cluster2: 1 core */
+	{ 2, 0 },
+	/* Cluster3: 1 core */
+	{ 3, 0 },
+	/* Cluster4: 1 core */
+	{ 4, 0 },
+	/* Cluster5: 1 core */
+	{ 5, 0 },
+	/* Cluster6: 1 core */
+	{ 6, 0 },
+	/* Cluster7: 1 core */
+	{ 7, 0 },
+	/* Cluster8: 1 core */
+	{ 8, 0 },
+	/* Cluster9: 1 core */
+	{ 9, 0 },
+	/* Cluster10: 1 core */
+	{ 10, 0 },
+	/* Cluster11: 1 core */
+	{ 11, 0 },
+	/* Cluster12: 1 core */
+	{ 12, 0 },
+	/* Cluster13: 1 core */
+	{ 13, 0 },
+	/* Cluster14: 1 core */
+	{ 14, 0 },
+	/* Cluster15: 1 core */
+	{ 15, 0 },
+};
+
+/*
+ * The power domain tree descriptor. The cluster power domains are
+ * arranged so that when the PSCI generic code creates the power domain tree,
+ * the indices of the CPU power domain nodes it allocates match the linear
+ * indices returned by plat_core_pos_by_mpidr().
+ */
+const unsigned char plat_pd_tree_desc[] = {
+	/* Number of root nodes */
+	PLAT_ARM_CLUSTER_COUNT,
+	/* Number of children for the 1st node */
+	NRD_MAX_CPUS_PER_CLUSTER,
+	/* Number of children for the 2nd node */
+	NRD_MAX_CPUS_PER_CLUSTER,
+	/* Number of children for the 3rd node */
+	NRD_MAX_CPUS_PER_CLUSTER,
+	/* Number of children for the 4th node */
+	NRD_MAX_CPUS_PER_CLUSTER,
+	/* Number of children for the 5th node */
+	NRD_MAX_CPUS_PER_CLUSTER,
+	/* Number of children for the 6th node */
+	NRD_MAX_CPUS_PER_CLUSTER,
+	/* Number of children for the 7th node */
+	NRD_MAX_CPUS_PER_CLUSTER,
+	/* Number of children for the 8th node */
+	NRD_MAX_CPUS_PER_CLUSTER,
+	/* Number of children for the 9th node */
+	NRD_MAX_CPUS_PER_CLUSTER,
+	/* Number of children for the 10th node */
+	NRD_MAX_CPUS_PER_CLUSTER,
+	/* Number of children for the 11th node */
+	NRD_MAX_CPUS_PER_CLUSTER,
+	/* Number of children for the 12th node */
+	NRD_MAX_CPUS_PER_CLUSTER,
+	/* Number of children for the 13th node */
+	NRD_MAX_CPUS_PER_CLUSTER,
+	/* Number of children for the 14th node */
+	NRD_MAX_CPUS_PER_CLUSTER,
+	/* Number of children for the 15th node */
+	NRD_MAX_CPUS_PER_CLUSTER,
+	/* Number of children for the 16th node */
+	NRD_MAX_CPUS_PER_CLUSTER
+};
+
+const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
+{
+	return plat_pd_tree_desc;
+}
+
+uint64_t tftf_plat_get_mpidr(unsigned int core_pos)
+{
+	unsigned int mpid;
+
+	assert(core_pos < PLATFORM_CORE_COUNT);
+
+	mpid = make_mpid(plat_cores[core_pos].cluster_id,
+				plat_cores[core_pos].cpu_id);
+
+	return (uint64_t)mpid;
+}
\ No newline at end of file