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review.trustedfirmware.org / TF-A / tf-a-tests / fc0b20764ec1d613ae41f7985485d8be81c5e526 / . / tftf / framework / aarch32 / entrypoint.S
blob: 1f302fa84a6473aee4029444e0eb6bc9460bd6c8 [file] [log] [blame]
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]1/*
2 * Copyright (c) 2018, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <tftf.h>
10
11 .globl tftf_entrypoint
12 .globl tftf_hotplug_entry
13
14/* ----------------------------------------------------------------------------
15 * Cold boot entry point for the primary CPU.
16 * ----------------------------------------------------------------------------
17 */
18func tftf_entrypoint
Sandrine Bailleux39caa2c2018-12-18 10:53:34 +0100[diff] [blame]19 bl arch_init
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]20
21 /* --------------------------------------------------------------------
22 * This code is expected to be executed only by the primary CPU.
23 * Save the mpid for the first core that executes and if a secondary
24 * CPU has lost its way make it spin forever.
25 * --------------------------------------------------------------------
26 */
27 bl save_primary_mpid
28
29 /* --------------------------------------------------------------------
30 * Zero out NOBITS sections. There are 2 of them:
31 * - the .bss section;
32 * - the coherent memory section.
33 * --------------------------------------------------------------------
34 */
35 ldr r0, =__BSS_START__
36 ldr r1, =__BSS_SIZE__
37 bl zeromem
38
39 ldr r0, =__COHERENT_RAM_START__
40 ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__
41 bl zeromem
42
43 /* --------------------------------------------------------------------
44 * Give ourselves a small coherent stack to ease the pain of
45 * initializing the MMU
46 * --------------------------------------------------------------------
47 */
48 ldcopr r0, MPIDR
49 bl platform_set_coherent_stack
50
51 bl tftf_early_platform_setup
52 bl tftf_plat_arch_setup
53
54 /* --------------------------------------------------------------------
55 * Give ourselves a stack allocated in Normal -IS-WBWA memory
56 * --------------------------------------------------------------------
57 */
58 ldcopr r0, MPIDR
59 bl platform_set_stack
60
61 /* --------------------------------------------------------------------
62 * tftf_cold_boot_main() will perform the remaining architectural and
63 * platform setup, initialise the test framework's state, then run the
64 * tests.
65 * --------------------------------------------------------------------
66 */
67 b tftf_cold_boot_main
68endfunc tftf_entrypoint
69
70/* ----------------------------------------------------------------------------
71 * Entry point for a CPU that has just been powered up.
72 * In : r0 - context_id
73 * ----------------------------------------------------------------------------
74 */
75func tftf_hotplug_entry
76
77 /* --------------------------------------------------------------------
78 * Preserve the context_id in a callee-saved register
79 * --------------------------------------------------------------------
80 */
81 mov r4, r0
82
Sandrine Bailleux39caa2c2018-12-18 10:53:34 +0100[diff] [blame]83 bl arch_init
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]84
85 /* --------------------------------------------------------------------
86 * Give ourselves a small coherent stack to ease the pain of
87 * initializing the MMU
88 * --------------------------------------------------------------------
89 */
90 ldcopr r0, MPIDR
91 bl platform_set_coherent_stack
92
93 /* --------------------------------------------------------------------
94 * Enable the MMU
95 * --------------------------------------------------------------------
96 */
97 bl tftf_plat_enable_mmu
98
99 /* --------------------------------------------------------------------
100 * Give ourselves a stack in normal memory.
101 * --------------------------------------------------------------------
102 */
103 ldcopr r0, MPIDR
104 bl platform_set_stack
105
106 /* --------------------------------------------------------------------
107 * Save the context_id for later retrieval by tests
108 * --------------------------------------------------------------------
109 */
110 ldcopr r0, MPIDR
111 ldr r1, =MPID_MASK
112 and r0, r0, r1
113 bl platform_get_core_pos
114
115 mov r1, r4
116
117 bl tftf_set_cpu_on_ctx_id
118
119 /* --------------------------------------------------------------------
120 * Jump to warm boot main function
121 * --------------------------------------------------------------------
122 */
123 b tftf_warm_boot_main
124endfunc tftf_hotplug_entry
125
126/* ----------------------------------------------------------------------------
Sandrine Bailleux39caa2c2018-12-18 10:53:34 +0100[diff] [blame]127 * Initialize architectural state.
128 * ----------------------------------------------------------------------------
129 */
130func arch_init
131 /* Set the exception vectors. */
132 ldr r0, =tftf_vector
133 stcopr r0, HVBAR
134
135 /* Enable the instruction cache. */
136 ldr r0, =(HSCTLR_RES1 | HSCTLR_I_BIT)
137 stcopr r0, HSCTLR
138
139 isb
140 bx lr
141endfunc arch_init
142
143/* ----------------------------------------------------------------------------
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]144 * Saves the mpid of the primary core and if the primary core
145 * is already saved then it loops infinitely.
146 * ----------------------------------------------------------------------------
147 */
148func save_primary_mpid
149 ldr r1, =tftf_primary_core
150 ldr r0, [r1]
151 mov r2, #INVALID_MPID
152 cmp r0, r2
153 bne panic
154 ldr r2, =MPID_MASK
155 ldcopr r0, MPIDR
156 and r0, r0, r2
157 str r0, [r1]
158 bx lr
159panic:
160 /* Primary core MPID already saved */
161 b panic
162endfunc save_primary_mpid