fix(nxp-ddr): apply Max CDD values for warm boot

Timing CFG 0 and Timing CFG 4 are ddr controller registers that
have been affected by 1d phy training during cold boot. They are
needed to be stored and restored along with phy training values.

Signed-off-by: Maninder Singh <>
Signed-off-by: Jiafei Pan <>
Change-Id: I29c55256e74456515aaeb098e2e0e3475697a466
2 files changed