commit 02a9d70c4deaa2102386611ac6b305838003148d
author Sieu Mun Tang <sieu.mun.tang@intel.com> Thu Jun 23 18:05:02 2022 +0800
committer Sieu Mun Tang <sieu.mun.tang@intel.com> Fri Apr 14 09:17:33 2023 +0800
tree 1e5b1ab1162480a3fe009849015aa6ac8b029f7d
parent 15db5039b5ad8c77a62ad8b9aac0bf587681918d

feat(intel): implement timer init divider via CPU frequency for N5X

Get CPU frequency and update the timer init div with it.
The timer is vary based on the CPU frequency instead of hardcoded.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibfaa47fb7a25176eebf06f4828bf9729d56f12ed

plat/intel/soc/common/socfpga_delay_timer.c

diff --git a/plat/intel/soc/common/socfpga_delay_timer.c b/plat/intel/soc/common/socfpga_delay_timer.c
index dcd51e2..8fce5cf 100644
--- a/plat/intel/soc/common/socfpga_delay_timer.c
+++ b/plat/intel/soc/common/socfpga_delay_timer.c
@@ -10,6 +10,15 @@
 #include <lib/mmio.h>
 #include "socfpga_plat_def.h"
 
+
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
+#include "agilex_clock_manager.h"
+#elif PLATFORM_MODEL == PLAT_SOCFPGA_N5X
+#include "n5x_clock_manager.h"
+#elif PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
+#include "s10_clock_manager.h"
+#endif
+
 #define SOCFPGA_GLOBAL_TIMER		0xffd01000
 #define SOCFPGA_GLOBAL_TIMER_EN		0x3
 
@@ -43,6 +52,8 @@
 	socfpga_delay_timer_init_args();
 	mmio_write_32(SOCFPGA_GLOBAL_TIMER, SOCFPGA_GLOBAL_TIMER_EN);
 
+	NOTICE("BL31 CLK freq = %d MHz\n", PLAT_SYS_COUNTER_FREQ_IN_MHZ);
+
 	asm volatile("msr cntp_ctl_el0, %0" : : "r" (SOCFPGA_GLOBAL_TIMER_EN));
 	asm volatile("msr cntp_tval_el0, %0" : : "r" (~0));