| commit | 039b7d4673e5b39056a6c0c40204aad2b0258581 | [log] [tgz] |
|---|---|---|
| author | Patrick Delaunay <patrick.delaunay@foss.st.com> | Wed May 22 10:04:19 2024 +0200 |
| committer | Yann Gautier <yann.gautier@st.com> | Tue Jun 11 11:45:38 2024 +0200 |
| tree | 0f6584cdf1da166a75c542d0b58a9d4711bb579a | |
| parent | f4a2bb986b43fcb1c0c8c45b5d9a93798f655453 [diff] |
fix(st-clock): display proper PLL number for STM32MP13 The PLL clk_id does not start at 0, but it is in the enum listing all clocks. To have a better display of the PLL number, start at PLL1, by changing pll->clk_id in messages with pll->clk_id - _CK_PLL1 + 1. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Change-Id: Ic09195ae6fe5f8d3a87e69962425f7c826f3670b