commit 0ad5b318f7e8e7ff35b5e607e3d11c31efeb3872
author Madhukar Pappireddy <madhukar.pappireddy@arm.com> Thu Feb 13 15:36:50 2020 -0600
committer Madhukar Pappireddy <madhukar.pappireddy@arm.com> Thu Feb 13 15:45:06 2020 -0600
tree e135b9ce756e2f067cc3bc82ea55c6705e1f4808
parent 572fcdd547753d668ca1146ca420664ccc3ac6fb

Fix topology description of cpus for DynamIQ based FVP

DynamIQ based designs have upto 8 CPUs in each cluster. This
patch fixes the device tree node which describes the topology
of the CPU for DynamIQ FVP Model.

Change-Id: I7146bc79029ce38314026d4853e5b6406863725c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

fdts/fvp-base-gicv3-psci-dynamiq-2t.dts

diff --git a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
index 48269a0..daa2e66 100644
--- a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
+++ b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include "fvp-base-gicv3-psci-common.dtsi"
+#include "fvp-base-gicv3-psci-dynamiq-common.dtsi"
 
 &CPU0 {
 	reg = <0x0 0x0>;