| commit | 100d4029a926a7d0df28072d9674787c09e37d85 | [log] [tgz] |
|---|---|---|
| author | johpow01 <john.powell@arm.com> | Tue Aug 03 14:35:20 2021 -0500 |
| committer | John <john.powell@arm.com> | Tue Aug 10 17:23:01 2021 +0200 |
| tree | a62ca829edaa2bcfe71a6df80b348d78ac500455 | |
| parent | 1a8804c3834966f8177eb9211bb24f546420ba9b [diff] [blame] |
errata: workaround for Neoverse V1 errata 2139242 Neoverse V1 erratum 2139242 is a Cat B erratum present in the V1 processor core. This issue is present in revisions r0p0, r1p0, and r1p1, and it is still open. SDEN can be found here: https://documentation-service.arm.com/static/60d499080320e92fa40b4625 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I5c2e9beec72a64ac4131fb6dd76199821a934ebe
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 4d7b179..bc277a7 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst
@@ -349,6 +349,10 @@ issue is present in r0p0 as well but there is no workaround for that revision. It is still open. +- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1 + CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the + CPU. It is still open. + DSU Errata Workarounds ----------------------