feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge
This adds F2S and S2F bridge enable, disable and reset
sequence to enable, disable and reset properly the bridges
in SMC call or during reset.
The reset is also maskable as the SMC from uboot can
pass in the bridge mask when requesting for bridge
enable or disable.
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ie144518c591664ef880016c9b3706968411bbf21
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index f22c2ee..79444cf 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -105,7 +105,7 @@
}
if (bridge_disable) {
- socfpga_bridges_enable(); /* Enable bridge */
+ socfpga_bridges_enable(~0); /* Enable bridge */
bridge_disable = false;
}
@@ -241,7 +241,7 @@
/* Disable bridge on full reconfiguration */
if (bridge_disable) {
- socfpga_bridges_disable();
+ socfpga_bridges_disable(~0);
}
return INTEL_SIP_SMC_STATUS_OK;
@@ -527,12 +527,26 @@
}
/* Miscellaneous HPS services */
-static uint32_t intel_hps_set_bridges(uint64_t enable)
+uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask)
{
- if (enable != 0U) {
- socfpga_bridges_enable();
+ int status = 0;
+
+ if (enable & SOCFPGA_BRIDGE_ENABLE) {
+ if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0) {
+ status = socfpga_bridges_enable((uint32_t)mask);
+ } else {
+ status = socfpga_bridges_enable(~0);
+ }
} else {
- socfpga_bridges_disable();
+ if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0) {
+ status = socfpga_bridges_disable((uint32_t)mask);
+ } else {
+ status = socfpga_bridges_disable(~0);
+ }
+ }
+
+ if (status < 0) {
+ return INTEL_SIP_SMC_STATUS_ERROR;
}
return INTEL_SIP_SMC_STATUS_OK;
@@ -697,6 +711,10 @@
status = intel_smc_get_usercode(&retval);
SMC_RET2(handle, status, retval);
+ case INTEL_SIP_SMC_HPS_SET_BRIDGES:
+ status = intel_hps_set_bridges(x1, x2);
+ SMC_RET1(handle, status);
+
case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384:
status = intel_fcs_get_rom_patch_sha384(x1, &retval64,
&mbox_error);
@@ -707,10 +725,6 @@
SIP_SVC_VERSION_MAJOR,
SIP_SVC_VERSION_MINOR);
- case INTEL_SIP_SMC_HPS_SET_BRIDGES:
- status = intel_hps_set_bridges(x1);
- SMC_RET1(handle, status);
-
case INTEL_SIP_SMC_HWMON_READTEMP:
status = intel_hwmon_readtemp(x1, &retval);
SMC_RET2(handle, status, retval);