tree 173315ffb49b9727d3cc27976378956245ee30c2
parent e434cf1aa3548e943d43a5ae72b65fd9d9633b84
author Soby Mathew <soby.mathew@arm.com> 1408630827 +0100
committer Soby Mathew <soby.mathew@arm.com> 1408635025 +0100

Rationalize UART usage among different BL stages

This patch changes the UART port assignment for various BL stages
so as to make it consistent on the platform ports. The BL1, BL2 and
BL3-1 now uses UART0 on the FVP port and SoC UART0 on the Juno port.
The BL3-2 uses UART2 on the FVP port and FPGA UART0 on the Juno
port.

This provides an interim fix to ARM-software/tf-issues#220 until
support is added for changing the UART port for a BL image between
cold boot and runtime.

Change-Id: Iae5faea90be3d59e41e597b34a902f93e737505a