fix(gpt): correct the GPC enable sequence

Since GPC control register fields are permitted to be cached in a TLB,
invalidate TLB after setting fields to ensure future checks are using
the updated values.

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I95630b40b673363bbf74da2705deca03089fff3a
diff --git a/lib/gpt_rme/gpt_rme.c b/lib/gpt_rme/gpt_rme.c
index e001e5f..a6e17a3 100644
--- a/lib/gpt_rme/gpt_rme.c
+++ b/lib/gpt_rme/gpt_rme.c
@@ -693,10 +693,6 @@
 		return -EPERM;
 	}
 
-	/* Invalidate any stale TLB entries */
-	tlbipaallos();
-	dsb();
-
 	/* Write the base address of the L0 tables into GPTBR */
 	write_gptbr_el3(((gpt_config.plat_gpt_l0_base >> GPTBR_BADDR_VAL_SHIFT)
 			>> GPTBR_BADDR_SHIFT) & GPTBR_BADDR_MASK);
@@ -718,6 +714,15 @@
 	gpccr_el3 |= SET_GPCCR_ORGN(GPCCR_ORGN_WB_RA_WA);
 	gpccr_el3 |= SET_GPCCR_IRGN(GPCCR_IRGN_WB_RA_WA);
 
+	/* Prepopulate GPCCR_EL3 but don't enable GPC yet */
+	write_gpccr_el3(gpccr_el3);
+	isb();
+
+	/* Invalidate any stale TLB entries and any cached register fields */
+	tlbipaallos();
+	dsb();
+	isb();
+
 	/* Enable GPT */
 	gpccr_el3 |= GPCCR_GPC_BIT;