intel: Refactor common platform code [5/5]
Removes unused source code for BL2 and BL31 in platform.mk.
Clean-up unused header files, syntax fixes, and alphabetical
sorting post-refactoring
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ie5ea9b4d3abdb0187cddeb04d2fcfb51fbe5c4dd
diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c
index ece7b9c..86b7ab8 100644
--- a/plat/intel/soc/agilex/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex/bl2_plat_setup.c
@@ -14,14 +14,12 @@
#include <drivers/synopsys/dw_mmc.h>
#include <drivers/ti/uart/uart_16550.h>
#include <lib/xlat_tables/xlat_tables.h>
-#include <platform_def.h>
#include "agilex_clock_manager.h"
#include "agilex_memory_controller.h"
#include "agilex_pinmux.h"
#include "agilex_reset_manager.h"
#include "agilex_system_manager.h"
-
#include "ccu/ncore_ccu.h"
#include "qspi/cadence_qspi.h"
#include "socfpga_handoff.h"
diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c
index e7852cf..375483d 100644
--- a/plat/intel/soc/agilex/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex/bl31_plat_setup.c
@@ -12,7 +12,6 @@
#include <drivers/arm/gicv2.h>
#include <drivers/ti/uart/uart_16550.h>
#include <lib/xlat_tables/xlat_tables.h>
-#include <platform_def.h>
static entry_point_info_t bl32_image_ep_info;
@@ -104,7 +103,7 @@
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS),
MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS),
- {0},
+ {0}
};
/*******************************************************************************
@@ -126,7 +125,7 @@
BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
MT_DEVICE | MT_RW | MT_SECURE),
#endif
- {0},
+ {0}
};
setup_page_tables(bl_regions, plat_agilex_mmap);
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk
index dc56ac8..ef02a8d 100644
--- a/plat/intel/soc/agilex/platform.mk
+++ b/plat/intel/soc/agilex/platform.mk
@@ -4,7 +4,7 @@
#
# SPDX-License-Identifier: BSD-3-Clause
#
-#
+
PLAT_INCLUDES := \
-Iplat/intel/soc/agilex/include/ \
-Iplat/intel/soc/common/drivers/ \
@@ -25,28 +25,26 @@
BL2_SOURCES += \
common/desc_image_load.c \
- drivers/partition/partition.c \
- drivers/partition/gpt.c \
- drivers/arm/pl061/pl061_gpio.c \
drivers/mmc/mmc.c \
- drivers/synopsys/emmc/dw_mmc.c \
+ drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
drivers/io/io_storage.c \
drivers/io/io_block.c \
drivers/io/io_fip.c \
- drivers/gpio/gpio.c \
- drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
+ drivers/partition/partition.c \
+ drivers/partition/gpt.c \
+ drivers/synopsys/emmc/dw_mmc.c \
lib/cpus/aarch64/cortex_a53.S \
plat/intel/soc/agilex/bl2_plat_setup.c \
- plat/intel/soc/common/socfpga_storage.c \
- plat/intel/soc/common/bl2_plat_mem_params_desc.c \
- plat/intel/soc/agilex/soc/agilex_reset_manager.c \
plat/intel/soc/agilex/soc/agilex_clock_manager.c \
- plat/intel/soc/agilex/soc/agilex_pinmux.c \
plat/intel/soc/agilex/soc/agilex_memory_controller.c \
- plat/intel/soc/common/soc/socfpga_handoff.c \
+ plat/intel/soc/agilex/soc/agilex_pinmux.c \
+ plat/intel/soc/agilex/soc/agilex_reset_manager.c \
+ plat/intel/soc/agilex/soc/agilex_system_manager.c \
+ plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/common/socfpga_image_load.c \
- plat/intel/soc/agilex/soc/agilex_system_manager.c \
+ plat/intel/soc/common/socfpga_storage.c \
+ plat/intel/soc/common/soc/socfpga_handoff.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
plat/intel/soc/common/drivers/wdt/watchdog.c \
@@ -54,18 +52,14 @@
BL31_SOURCES += \
drivers/arm/cci/cci.c \
- lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/aem_generic.S \
+ lib/cpus/aarch64/cortex_a53.S \
plat/common/plat_psci_common.c \
- plat/intel/soc/common/socfpga_sip_svc.c \
plat/intel/soc/agilex/bl31_plat_setup.c \
plat/intel/soc/common/socfpga_psci.c \
+ plat/intel/soc/common/socfpga_sip_svc.c \
plat/intel/soc/common/socfpga_topology.c \
- plat/intel/soc/common/socfpga_delay_timer.c \
- plat/intel/soc/agilex/soc/agilex_reset_manager.c \
- plat/intel/soc/agilex/soc/agilex_pinmux.c \
- plat/intel/soc/agilex/soc/agilex_clock_manager.c \
- plat/intel/soc/common/soc/socfpga_mailbox.c
+ plat/intel/soc/common/soc/socfpga_mailbox.c \
PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1