Initialise CPU contexts from entry_point_info
Consolidate all BL3-1 CPU context initialization for cold boot, PSCI
and SPDs into two functions:
* The first uses entry_point_info to initialize the relevant
cpu_context for first entry into a lower exception level on a CPU
* The second populates the EL1 and EL2 system registers as needed
from the cpu_context to ensure correct entry into the lower EL
This patch alters the way that BL3-1 determines which exception level
is used when first entering EL1 or EL2 during cold boot - this is now
fully determined by the SPSR value in the entry_point_info for BL3-3,
as set up by the platform code in BL2 (or otherwise provided to BL3-1).
In the situation that EL1 (or svc mode) is selected for a processor
that supports EL2, the context management code will now configure all
essential EL2 register state to ensure correct execution of EL1. This
allows the platform code to run non-secure EL1 payloads directly
without requiring a small EL2 stub or OS loader.
Change-Id: If9fbb2417e82d2226e47568203d5a369f39d3b0f
diff --git a/services/std_svc/psci/psci_afflvl_on.c b/services/std_svc/psci/psci_afflvl_on.c
index e4d8f1f..d91db96 100644
--- a/services/std_svc/psci/psci_afflvl_on.c
+++ b/services/std_svc/psci/psci_afflvl_on.c
@@ -75,8 +75,10 @@
unsigned long ns_entrypoint,
unsigned long context_id)
{
- unsigned int index, plat_state;
+ unsigned int plat_state;
unsigned long psci_entrypoint;
+ uint32_t ns_scr_el3 = read_scr_el3();
+ uint32_t ns_sctlr_el1 = read_sctlr_el1();
int rc;
/* Sanity check to safeguard against data corruption */
@@ -103,8 +105,8 @@
* the non-secure world from the non-secure state from
* where this call originated.
*/
- index = cpu_node->data;
- rc = psci_set_ns_entry_info(index, ns_entrypoint, context_id);
+ rc = psci_save_ns_entry(target_cpu, ns_entrypoint, context_id,
+ ns_scr_el3, ns_sctlr_el1);
if (rc != PSCI_E_SUCCESS)
return rc;
@@ -336,7 +338,7 @@
static unsigned int psci_afflvl0_on_finish(unsigned long mpidr,
aff_map_node_t *cpu_node)
{
- unsigned int index, plat_state, state, rc = PSCI_E_SUCCESS;
+ unsigned int plat_state, state, rc;
assert(cpu_node->level == MPIDR_AFFLVL0);
@@ -383,11 +385,9 @@
/*
* Generic management: Now we just need to retrieve the
* information that we had stashed away during the cpu_on
- * call to set this cpu on its way. First get the index
- * for restoring the re-entry info
+ * call to set this cpu on its way.
*/
- index = cpu_node->data;
- psci_get_ns_entry_info(index);
+ cm_prepare_el3_exit(NON_SECURE);
/* State management: mark this cpu as on */
psci_set_state(cpu_node, PSCI_STATE_ON);
@@ -395,6 +395,7 @@
/* Clean caches before re-entering normal world */
dcsw_op_louis(DCCSW);
+ rc = PSCI_E_SUCCESS;
return rc;
}