errata: workaround for Neoverse V1 errata 1940577
Neoverse V1 erratum 1940577 is a Cat B erratum, present in some
revisions of the V1 processor core. The workaround is to insert a
DMB ST before acquire atomic instructions without release semantics.
This issue is present in revisions r0p0 - r1p1 but this workaround
only applies to revisions r1p0 - r1p1, there is no workaround for older
versions.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I210ad7d8f31c81b6ac51b028dfbce75a725c11aa
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 8d17d35..949845a 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -329,6 +329,10 @@
CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
in r1p1.
+- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1
+ CPU. This needs to be enabled only for revision r1p0 and r1p1 of the
+ CPU.
+
DSU Errata Workarounds
----------------------