diff --git a/plat/arm/board/arm_fpga/fpga_gicv3.c b/plat/arm/board/arm_fpga/fpga_gicv3.c
index be1684e..9fb5fa9 100644
--- a/plat/arm/board/arm_fpga/fpga_gicv3.c
+++ b/plat/arm/board/arm_fpga/fpga_gicv3.c
@@ -4,9 +4,13 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <common/debug.h>
+#include <common/fdt_wrappers.h>
 #include <drivers/arm/gicv3.h>
 #include <drivers/arm/gic_common.h>
+#include <libfdt.h>
 
+#include <platform_def.h>
 #include <plat/common/platform.h>
 #include <platform_def.h>
 
@@ -22,9 +26,7 @@
 	return (unsigned int)plat_core_pos_by_mpidr(mpidr);
 }
 
-static const gicv3_driver_data_t fpga_gicv3_driver_data = {
-	.gicd_base = GICD_BASE,
-	.gicr_base = GICR_BASE,
+static gicv3_driver_data_t fpga_gicv3_driver_data = {
 	.interrupt_props = fpga_interrupt_props,
 	.interrupt_props_num = ARRAY_SIZE(fpga_interrupt_props),
 	.rdistif_num = PLATFORM_CORE_COUNT,
@@ -34,6 +36,30 @@
 
 void plat_fpga_gic_init(void)
 {
+	const void *fdt = (void *)(uintptr_t)FPGA_PRELOADED_DTB_BASE;
+	int node, ret;
+
+	node = fdt_node_offset_by_compatible(fdt, 0, "arm,gic-v3");
+	if (node < 0) {
+		WARN("No \"arm,gic-v3\" compatible node found in DT, no GIC support.\n");
+		return;
+	}
+
+	/* TODO: Assuming only empty "ranges;" properties up the bus path. */
+	ret = fdt_get_reg_props_by_index(fdt, node, 0,
+				 &fpga_gicv3_driver_data.gicd_base, NULL);
+	if (ret < 0) {
+		WARN("Could not read GIC distributor address from DT.\n");
+		return;
+	}
+
+	ret = fdt_get_reg_props_by_index(fdt, node, 1,
+				 &fpga_gicv3_driver_data.gicr_base, NULL);
+	if (ret < 0) {
+		WARN("Could not read GIC redistributor address from DT.\n");
+		return;
+	}
+
 	gicv3_driver_init(&fpga_gicv3_driver_data);
 	gicv3_distif_init();
 	gicv3_rdistif_init(plat_my_core_pos());
diff --git a/plat/arm/board/arm_fpga/include/platform_def.h b/plat/arm/board/arm_fpga/include/platform_def.h
index 37f3d8a..31fc987 100644
--- a/plat/arm/board/arm_fpga/include/platform_def.h
+++ b/plat/arm/board/arm_fpga/include/platform_def.h
@@ -35,9 +35,6 @@
 #define BL31_LIMIT			UL(0x01000000)
 #endif
 
-#define GICD_BASE			0x30000000
-#define GICR_BASE			0x30040000
-
 #define PLAT_SDEI_NORMAL_PRI		0x70
 
 #define ARM_IRQ_SEC_PHY_TIMER		29