commit 2017ab241c6634ecc184f09a39e77a06146403b0
author lauwal01 <lauren.wehrmeister@arm.com> Mon Jun 24 11:32:40 2019 -0500
committer lauwal01 <lauren.wehrmeister@arm.com> Tue Jul 02 09:15:15 2019 -0500
tree 2df7811cdcf4159d4c36de40a65b57ed825e4811
parent e34606f2e400c192bac3abeb9b2053b2c91ccd7c

Workaround for Neoverse N1 erratum 1165347

Neoverse N1 erratum 1165347 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the implementation defined
CPUACTLR2_EL1 system register.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

docs/design/cpu-specific-build-macros.rst

diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 01ee416..fd99d8e 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -234,6 +234,9 @@
 -  ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1
    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
 
+-  ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
+
 -  ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.