commit 256d133a8a489b8731e5f499457468a4b8a13ab4
author Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Mon Sep 24 22:51:49 2018 -0700
committer Jolly Shah <jolly.shah@xilinx.com> Wed Jan 15 11:01:23 2020 -0800
tree 19deca09a64471103eed91aa36a0233f4f3da441
parent fe550edef034ec6b9c4564a0b9c27136a7df5968

plat: xilinx: zynqmp: Use GIC framework for warm restart

- Flag GICV2_G0_FOR_EL3 needs to be set for group interrupts
  to be targeted to EL3.
- Raise SGI interrupts for individual CPU cores as GIC API
  uses CPU num as parameter, not CPU mask.
- Flag WARMBOOT_ENABLE_DCACHE_EARLY needs to be set to enable
  CPU interface mask work properly for all CPU cores which is
  required when generating SGI.
- Call plat_ic_end_of_interrupt() from ttc_fiq_handler() to clear
  GIC interrupt to avoid same interrupt again.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I71d4935b8d4688a3729c62753ca8a1a77cd92ae7

plat/xilinx/zynqmp/platform.mk

diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 1039e27..33d6488 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -11,6 +11,8 @@
 ZYNQMP_WDT_RESTART := 0
 ZYNQMP_IPI_CRC_CHECK := 0
 override RESET_TO_BL31 := 1
+override GICV2_G0_FOR_EL3 := 1
+override WARMBOOT_ENABLE_DCACHE_EARLY := 1
 
 # Do not enable SVE
 ENABLE_SVE_FOR_NS	:= 0