Tegra: remove support for SEPARATE_CODE_AND_RODATA=0
Tegra platforms will not be supporting SEPARATE_CODE_AND_RODATA=0.
This patch uses the common macros provided by bl_common.h as a result
and adds a check to assert if SEPARATE_CODE_AND_RODATA set is not set
to '1'.
Change-Id: I376ea60c00ad69cb855d89418bdb80623f14800e
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 46686c3..0589077 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -39,15 +39,8 @@
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
******************************************************************************/
-
IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START);
-static const uint64_t BL31_RW_END = BL_END;
-static const uint64_t BL31_RODATA_BASE = BL_RO_DATA_BASE;
-static const uint64_t BL31_RODATA_END = BL_RO_DATA_END;
-static const uint64_t TEXT_START = BL_CODE_BASE;
-static const uint64_t TEXT_END = BL_CODE_END;
-
extern uint64_t tegra_bl31_phys_base;
static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
@@ -314,11 +307,11 @@
void bl31_plat_arch_setup(void)
{
uint64_t rw_start = BL31_RW_START;
- uint64_t rw_size = BL31_RW_END - BL31_RW_START;
- uint64_t rodata_start = BL31_RODATA_BASE;
- uint64_t rodata_size = BL31_RODATA_END - BL31_RODATA_BASE;
- uint64_t code_base = TEXT_START;
- uint64_t code_size = TEXT_END - TEXT_START;
+ uint64_t rw_size = BL_END - BL31_RW_START;
+ uint64_t rodata_start = BL_RO_DATA_BASE;
+ uint64_t rodata_size = BL_RO_DATA_END - BL_RO_DATA_BASE;
+ uint64_t code_base = BL_CODE_BASE;
+ uint64_t code_size = BL_CODE_END - BL_CODE_BASE;
const mmap_region_t *plat_mmio_map = NULL;
#if USE_COHERENT_MEM
uint32_t coh_start, coh_size;