)]}' { "commit": "2c265975a76977c6373636f5f28e114d1b73e10e", "tree": "4bdf0f602225aa23fd6ab74ea2714e0098a77e74", "parents": [ "764aa951b2ca451694c74791964a712d423d8206" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jul 19 14:35:00 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Thu Oct 06 14:02:25 2022 +0100" }, "message": "feat(drtm): invalidate icache before DLME launch\n\nAs per DRTM beta0 spec table #28, Before the DLME is called the DCE\nmust invalidate all instruction caches.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I7efbb03d1d13346a8d898882fdbd7bbe8f1d49b2\n", "tree_diff": [ { "type": "modify", "old_id": "443516d286e9c3f9143c7fce3fe889069f23110b", "old_mode": 33188, "old_path": "services/std_svc/drtm/drtm_main.c", "new_id": "c98d829b3deaad401e8b0692fef5a4f7c014313a", "new_mode": 33188, "new_path": "services/std_svc/drtm/drtm_main.c" } ] }