board/rdn1edge: add support for dual-chip configuration
RD-N1-Edge based platforms can operate in dual-chip configuration
wherein two rdn1edge SoCs are connected through a high speed coherent
CCIX link.
This patch adds a function to check if the RD-N1-Edge platform is
operating in multi-chip mode by reading the SID register's NODE_ID
value. If operating in multi-chip mode, initialize GIC-600 multi-chip
operation by overriding the default GICR frames with array of GICR
frames and setting the chip 0 as routing table owner.
The address space of the second RD-N1-Edge chip (chip 1) starts from the
address 4TB. So increase the physical and virtual address space size to
43 bits to accommodate the multi-chip configuration. If the multi-chip
mode configuration is detected, dynamically add mmap entry for the
peripherals memory region of the second RD-N1-Edge SoC. This is required
to let the BL31 platform setup stage to configure the devices in the
second chip.
PLATFORM_CORE_COUNT macro is set to be multiple of CSS_SGI_CHIP_COUNT
and topology changes are added to represent the dual-chip configuration.
In order the build the dual-chip platform, CSS_SGI_CHIP_COUNT macro
should be set to 2:
export CROSS_COMPILE=<path-to-cross-compiler>
make PLAT=rdn1edge CSS_SGI_CHIP_COUNT=2 ARCH=aarch64 all
Change-Id: I576cdaf71f0b0e41b9a9181fa4feb7091f8c7bb4
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c
index 3d2d933..f5d0f41 100644
--- a/plat/arm/css/sgi/sgi_bl31_setup.c
+++ b/plat/arm/css/sgi/sgi_bl31_setup.c
@@ -28,18 +28,56 @@
.ring_doorbell = &mhu_ring_doorbell,
};
-static scmi_channel_plat_info_t rd_n1e1_edge_scmi_plat_info = {
+static scmi_channel_plat_info_t rd_n1e1_edge_scmi_plat_info[] = {
+ {
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
.db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
.db_preserve_mask = 0xfffffffe,
.db_modify_mask = 0x1,
.ring_doorbell = &mhuv2_ring_doorbell,
+ },
+ #if (CSS_SGI_CHIP_COUNT > 1)
+ {
+ .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
+ CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
+ .db_reg_addr = PLAT_CSS_MHU_BASE
+ + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1) + SENDER_REG_SET(0),
+ .db_preserve_mask = 0xfffffffe,
+ .db_modify_mask = 0x1,
+ .ring_doorbell = &mhuv2_ring_doorbell,
+ },
+ #endif
+ #if (CSS_SGI_CHIP_COUNT > 2)
+ {
+ .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
+ CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
+ .db_reg_addr = PLAT_CSS_MHU_BASE +
+ CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2) + SENDER_REG_SET(0),
+ .db_preserve_mask = 0xfffffffe,
+ .db_modify_mask = 0x1,
+ .ring_doorbell = &mhuv2_ring_doorbell,
+ },
+ #endif
+ #if (CSS_SGI_CHIP_COUNT > 3)
+ {
+ .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
+ CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
+ .db_reg_addr = PLAT_CSS_MHU_BASE +
+ CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3) + SENDER_REG_SET(0),
+ .db_preserve_mask = 0xfffffffe,
+ .db_modify_mask = 0x1,
+ .ring_doorbell = &mhuv2_ring_doorbell,
+ },
+ #endif
};
scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
{
- if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM)
- return &rd_n1e1_edge_scmi_plat_info;
+ if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) {
+ if (channel_id >= sizeof(rd_n1e1_edge_scmi_plat_info))
+ panic();
+ return &rd_n1e1_edge_scmi_plat_info[channel_id];
+ }
else if (sgi_plat_info.platform_id == SGI575_SSC_VER_PART_NUM)
return &sgi575_scmi_plat_info;
else