diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index 7eea22f..aa1ae67 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -112,7 +112,7 @@
 ----------------
 
 TF-A has been tested with pre-built binaries and file systems from `Linaro
-Release 19.06`_. Alternatively, you can build the binaries from source using
+Release 20.01`_. Alternatively, you can build the binaries from source using
 instructions in :ref:`Performing an Initial Build`.
 
 .. _prerequisites_get_source:
@@ -166,4 +166,4 @@
 .. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes
 .. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/arm-reference-platforms-deliverables
 .. _Development Studio 5 (DS-5): https://developer.arm.com/products/software-development-tools/ds-5-development-studio
-.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06
+.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst
index fb38d91..8e46083 100644
--- a/docs/plat/arm/fvp/index.rst
+++ b/docs/plat/arm/fvp/index.rst
@@ -101,7 +101,7 @@
    the models. The models can be launched with ``-Q 100`` option if they are
    required to match the run time characteristics of the older versions.
 
-All the above platforms have been tested with `Linaro Release 19.06`_.
+All the above platforms have been tested with `Linaro Release 20.01`_.
 
 .. _build_options_arm_fvp_platform:
 
@@ -649,5 +649,5 @@
 .. _TB_FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
 .. _Arm's website: `FVP models`_
 .. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
-.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06
+.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
 .. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms
diff --git a/drivers/arm/gic/v3/gicv3_helpers.c b/drivers/arm/gic/v3/gicv3_helpers.c
index 23a1dfa..a0f44e9 100644
--- a/drivers/arm/gic/v3/gicv3_helpers.c
+++ b/drivers/arm/gic/v3/gicv3_helpers.c
@@ -110,6 +110,28 @@
 	return spi_limit;
 }
 
+#if GIC_EXT_INTID
+/*******************************************************************************
+ * Helper function to get the maximum ESPI INTID + 1.
+ ******************************************************************************/
+unsigned int gicv3_get_espi_limit(uintptr_t gicd_base)
+{
+	unsigned int typer_reg = gicd_read_typer(gicd_base);
+
+	/* Check if extended SPI range is implemented */
+	if ((typer_reg & TYPER_ESPI) != 0U) {
+		/*
+		 * (maximum ESPI INTID + 1) is equal to
+		 * 32 * (GICD_TYPER.ESPI_range + 1) + 4096
+		 */
+		return ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
+			TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID;
+	}
+
+	return 0U;
+}
+#endif /* GIC_EXT_INTID */
+
 /*******************************************************************************
  * Helper function to configure the default attributes of (E)SPIs.
  ******************************************************************************/
@@ -119,19 +141,8 @@
 #if GIC_EXT_INTID
 	unsigned int num_eints;
 #endif
-	unsigned int typer_reg = gicd_read_typer(gicd_base);
 
-	/* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */
-	num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
-
-	/*
-	 * The GICv3 architecture allows GICD_TYPER.ITLinesNumber to be 31, so
-	 * the maximum possible value for num_ints is 1024. Limit the value to
-	 * MAX_SPI_ID + 1 to avoid getting wrong address in GICD_OFFSET() macro.
-	 */
-	if (num_ints > MAX_SPI_ID + 1U) {
-		num_ints = MAX_SPI_ID + 1U;
-	}
+	num_ints = gicv3_get_spi_limit(gicd_base);
 	INFO("Maximum SPI INTID supported: %u\n", num_ints - 1);
 
 	/* Treat all (E)SPIs as G1NS by default. We do 32 at a time. */
@@ -140,13 +151,8 @@
 	}
 
 #if GIC_EXT_INTID
-	/* Check if extended SPI range is implemented */
-	if ((typer_reg & TYPER_ESPI) != 0U) {
-		/*
-		 * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095
-		 */
-		num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
-			TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID;
+	num_eints = gicv3_get_espi_limit(gicd_base);
+	if (num_eints != 0U) {
 		INFO("Maximum ESPI INTID supported: %u\n", num_eints - 1);
 
 		for (i = MIN_ESPI_ID; i < num_eints;
@@ -154,7 +160,6 @@
 			gicd_write_igroupr(gicd_base, i, ~0U);
 		}
 	} else {
-		num_eints = 0U;
 		INFO("ESPI range is not implemented.\n");
 	}
 #endif
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index 5a49b4f..668416c 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -728,40 +728,17 @@
  *****************************************************************************/
 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)
 {
-	unsigned int typer_reg, num_ints;
-#if GIC_EXT_INTID
-	unsigned int num_eints;
-#endif
-
 	assert(gicv3_driver_data != NULL);
 	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(IS_IN_EL3());
 	assert(dist_ctx != NULL);
 
 	uintptr_t gicd_base = gicv3_driver_data->gicd_base;
-
-	typer_reg = gicd_read_typer(gicd_base);
-
-	/* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */
-	num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
-
-	/* Filter out special INTIDs 1020-1023 */
-	if (num_ints > (MAX_SPI_ID + 1U)) {
-		num_ints = MAX_SPI_ID + 1U;
-	}
-
+	unsigned int num_ints = gicv3_get_spi_limit(gicd_base);
 #if GIC_EXT_INTID
-	/* Check if extended SPI range is implemented */
-	if ((typer_reg & TYPER_ESPI) != 0U) {
-		/*
-		 * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095
-		 */
-		num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
-			TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID;
-	} else {
-		num_eints = 0U;
-	}
+	unsigned int num_eints = gicv3_get_espi_limit(gicd_base);
 #endif
+
 	/* Wait for pending write to complete */
 	gicd_wait_for_pending_write(gicd_base);
 
@@ -838,11 +815,6 @@
  *****************************************************************************/
 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
 {
-	unsigned int typer_reg, num_ints;
-#if GIC_EXT_INTID
-	unsigned int num_eints;
-#endif
-
 	assert(gicv3_driver_data != NULL);
 	assert(gicv3_driver_data->gicd_base != 0U);
 	assert(IS_IN_EL3());
@@ -864,27 +836,9 @@
 	/* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */
 	gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE);
 
-	typer_reg = gicd_read_typer(gicd_base);
-
-	/* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */
-	num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
-
-	/* Filter out special INTIDs 1020-1023 */
-	if (num_ints > (MAX_SPI_ID + 1U)) {
-		num_ints = MAX_SPI_ID + 1U;
-	}
-
+	unsigned int num_ints = gicv3_get_spi_limit(gicd_base);
 #if GIC_EXT_INTID
-	/* Check if extended SPI range is implemented */
-	if ((typer_reg & TYPER_ESPI) != 0U) {
-		/*
-		 * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095
-		 */
-		num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
-			TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID;
-	} else {
-		num_eints = 0U;
-	}
+	unsigned int num_eints = gicv3_get_espi_limit(gicd_base);
 #endif
 	/* Restore GICD_IGROUPR for INTIDs 32 - 1019 */
 	RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP);
diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h
index 7965f40..93ee1a1 100644
--- a/drivers/arm/gic/v3/gicv3_private.h
+++ b/drivers/arm/gic/v3/gicv3_private.h
@@ -234,6 +234,7 @@
  * Private GICv3 helper function prototypes
  ******************************************************************************/
 unsigned int gicv3_get_spi_limit(uintptr_t gicd_base);
+unsigned int gicv3_get_espi_limit(uintptr_t gicd_base);
 void gicv3_spis_config_defaults(uintptr_t gicd_base);
 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base);
 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
diff --git a/fdts/morello-fvp.dts b/fdts/morello-fvp.dts
index 4f6c8a7..55c87bf 100644
--- a/fdts/morello-fvp.dts
+++ b/fdts/morello-fvp.dts
@@ -27,33 +27,52 @@
 	cpus {
 		#address-cells = <2>;
 		#size-cells = <0>;
-		cpu0@0 {
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+				core1 {
+					cpu = <&CPU1>;
+				};
+			};
+			cluster1 {
+				core0 {
+					cpu = <&CPU2>;
+				};
+				core1 {
+					cpu = <&CPU3>;
+				};
+			};
+		};
+		CPU0: cpu0@0 {
 			compatible = "arm,armv8";
 			reg = <0x0 0x0>;
 			device_type = "cpu";
 			enable-method = "psci";
 			clocks = <&scmi_dvfs 0>;
 		};
-		cpu1@100 {
+		CPU1: cpu1@100 {
 			compatible = "arm,armv8";
 			reg = <0x0 0x100>;
 			device_type = "cpu";
 			enable-method = "psci";
 			clocks = <&scmi_dvfs 0>;
 		};
-		cpu2@10000 {
+		CPU2: cpu2@10000 {
 			compatible = "arm,armv8";
 			reg = <0x0 0x10000>;
 			device_type = "cpu";
 			enable-method = "psci";
-			clocks = <&scmi_dvfs 0>;
+			clocks = <&scmi_dvfs 1>;
 		};
-		cpu3@10100 {
+		CPU3: cpu3@10100 {
 			compatible = "arm,armv8";
 			reg = <0x0 0x10100>;
 			device_type = "cpu";
 			enable-method = "psci";
-			clocks = <&scmi_dvfs 0>;
+			clocks = <&scmi_dvfs 1>;
 		};
 	};
 
diff --git a/include/lib/smccc.h b/include/lib/smccc.h
index 470317d..deaeb1d 100644
--- a/include/lib/smccc.h
+++ b/include/lib/smccc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -51,6 +51,23 @@
 					 FUNCID_OEN_MASK)
 
 /*******************************************************************************
+ * SMCCC_ARCH_SOC_ID SoC version & revision bit definition
+ ******************************************************************************/
+#define SOC_ID_JEP_106_BANK_IDX_MASK	GENMASK_32(30, 24)
+#define SOC_ID_JEP_106_BANK_IDX_SHIFT	U(24)
+#define SOC_ID_JEP_106_ID_CODE_MASK	GENMASK_32(23, 16)
+#define SOC_ID_JEP_106_ID_CODE_SHIFT	U(16)
+#define SOC_ID_IMPL_DEF_MASK		GENMASK_32(15, 0)
+#define SOC_ID_IMPL_DEF_SHIFT		U(0)
+#define SOC_ID_SET_JEP_106(bkid, mfid)	((((bkid) << SOC_ID_JEP_106_BANK_IDX_SHIFT) & \
+					  SOC_ID_JEP_106_BANK_IDX_MASK) | \
+					 (((mfid) << SOC_ID_JEP_106_ID_CODE_SHIFT) & \
+					  SOC_ID_JEP_106_ID_CODE_MASK))
+
+#define SOC_ID_REV_MASK			GENMASK_32(30, 0)
+#define SOC_ID_REV_SHIFT		U(0)
+
+/*******************************************************************************
  * Owning entity number definitions inside the function id as per the SMC
  * calling convention
  ******************************************************************************/
diff --git a/include/plat/arm/common/smccc_def.h b/include/plat/arm/common/smccc_def.h
index 6e698e5..0f4e573 100644
--- a/include/plat/arm/common/smccc_def.h
+++ b/include/plat/arm/common/smccc_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,7 +9,5 @@
 /* Defines used to retrieve ARM SOC revision */
 #define ARM_SOC_CONTINUATION_CODE	U(0x4)
 #define ARM_SOC_IDENTIFICATION_CODE	U(0x3B)
-#define ARM_SOC_CONTINUATION_SHIFT	U(24)
-#define ARM_SOC_IDENTIFICATION_SHIFT	U(16)
 
 #endif /* SMCCC_DEF_H */
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 52686fa..fe0903b 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -483,9 +483,9 @@
 int32_t plat_get_soc_version(void)
 {
 	return (int32_t)
-		((ARM_SOC_IDENTIFICATION_CODE << ARM_SOC_IDENTIFICATION_SHIFT)
-		 | (ARM_SOC_CONTINUATION_CODE << ARM_SOC_CONTINUATION_SHIFT)
-		 | FVP_SOC_ID);
+		(SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE,
+				    ARM_SOC_IDENTIFICATION_CODE) |
+		 (FVP_SOC_ID & SOC_ID_IMPL_DEF_MASK));
 }
 
 /* Get SOC revision */
@@ -494,6 +494,6 @@
 	unsigned int sys_id;
 
 	sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
-	return (int32_t)((sys_id >> V2M_SYS_ID_REV_SHIFT) &
-			V2M_SYS_ID_REV_MASK);
+	return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) &
+			  V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK);
 }
diff --git a/plat/arm/board/juno/juno_common.c b/plat/arm/board/juno/juno_common.c
index cb183d5..038f604 100644
--- a/plat/arm/board/juno/juno_common.c
+++ b/plat/arm/board/juno/juno_common.c
@@ -118,9 +118,9 @@
 int32_t plat_get_soc_version(void)
 {
 	return (int32_t)
-		((ARM_SOC_IDENTIFICATION_CODE << ARM_SOC_IDENTIFICATION_SHIFT)
-		 | (ARM_SOC_CONTINUATION_CODE << ARM_SOC_CONTINUATION_SHIFT)
-		 | JUNO_SOC_ID);
+		(SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE,
+				    ARM_SOC_IDENTIFICATION_CODE) |
+		 (JUNO_SOC_ID & SOC_ID_IMPL_DEF_MASK));
 }
 
 /* Get SOC revision */
@@ -129,6 +129,6 @@
 	unsigned int sys_id;
 
 	sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
-	return (int32_t)((sys_id >> V2M_SYS_ID_REV_SHIFT) &
-			V2M_SYS_ID_REV_MASK);
+	return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) &
+			  V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK);
 }
diff --git a/plat/imx/imx8m/imx8m_psci_common.c b/plat/imx/imx8m/imx8m_psci_common.c
index dbb772d..9dfd311 100644
--- a/plat/imx/imx8m/imx8m_psci_common.c
+++ b/plat/imx/imx8m/imx8m_psci_common.c
@@ -152,19 +152,45 @@
 		req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE;
 }
 
-void __dead2 imx_system_reset(void)
+static void __dead2 imx_wdog_restart(bool external_reset)
 {
 	uintptr_t wdog_base = IMX_WDOG_BASE;
 	unsigned int val;
 
-	/* WDOG_B reset */
 	val = mmio_read_16(wdog_base);
-#ifdef IMX_WDOG_B_RESET
-	val = (val & 0x00FF) | WDOG_WCR_WDZST | WDOG_WCR_WDE |
-		WDOG_WCR_WDT | WDOG_WCR_SRS;
-#else
-	val = (val & 0x00FF) | WDOG_WCR_WDZST | WDOG_WCR_SRS;
-#endif
+	/*
+	 * Common watchdog init flags, for additional details check
+	 * 6.6.4.1 Watchdog Control Register (WDOGx_WCR)
+	 *
+	 * Initial bit selection:
+	 * WDOG_WCR_WDE - Enable the watchdog.
+	 *
+	 * 0x000E mask is used to keep previous values (that could be set
+	 * in SPL) of WDBG and WDE/WDT (both are write-one once-only bits).
+	 */
+	val = (val & 0x000E) | WDOG_WCR_WDE;
+	if (external_reset) {
+		/*
+		 * To assert WDOG_B (external reset) we have
+		 * to set WDA bit 0 (already set in previous step).
+		 * SRS bits are required to be set to 1 (no effect on the
+		 * system).
+		 */
+		val |= WDOG_WCR_SRS;
+	} else {
+		/*
+		 * To assert Software Reset Signal (internal reset) we have
+		 * to set SRS bit to 0 (already set in previous step).
+		 * SRE bit is required to be set to 1 when used in
+		 * conjunction with the Software Reset Signal before
+		 * SRS asserton, otherwise SRS bit will just automatically
+		 * reset to 1.
+		 *
+		 * Also we set WDA to 1 (no effect on system).
+		 */
+		val |= WDOG_WCR_SRE | WDOG_WCR_WDA;
+	}
+
 	mmio_write_16(wdog_base, val);
 
 	mmio_write_16(wdog_base + WDOG_WSR, 0x5555);
@@ -173,6 +199,27 @@
 		;
 }
 
+void __dead2 imx_system_reset(void)
+{
+#ifdef IMX_WDOG_B_RESET
+	imx_wdog_restart(true);
+#else
+	imx_wdog_restart(false);
+#endif
+}
+
+int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie)
+{
+	imx_wdog_restart(false);
+
+	/*
+	 * imx_wdog_restart cannot return (as it's  a __dead function),
+	 * however imx_system_reset2 has to return some value according
+	 * to PSCI v1.1 spec.
+	 */
+	return 0;
+}
+
 void __dead2 imx_system_off(void)
 {
 	mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, SNVS_LPCR_SRTC_ENV |
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_psci.c b/plat/imx/imx8m/imx8mm/imx8mm_psci.c
index e558724..815d3a2 100644
--- a/plat/imx/imx8m/imx8mm/imx8mm_psci.c
+++ b/plat/imx/imx8m/imx8mm/imx8mm_psci.c
@@ -28,6 +28,7 @@
 	.pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi,
 	.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
 	.system_reset = imx_system_reset,
+	.system_reset2 = imx_system_reset2,
 	.system_off = imx_system_off,
 };
 
diff --git a/plat/imx/imx8m/imx8mq/imx8mq_psci.c b/plat/imx/imx8m/imx8mq/imx8mq_psci.c
index 04e191f..662017d 100644
--- a/plat/imx/imx8m/imx8mq/imx8mq_psci.c
+++ b/plat/imx/imx8m/imx8mq/imx8mq_psci.c
@@ -117,6 +117,7 @@
 	.pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi,
 	.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
 	.system_reset = imx_system_reset,
+	.system_reset2 = imx_system_reset2,
 	.system_off = imx_system_off,
 };
 
diff --git a/plat/imx/imx8m/include/imx8m_psci.h b/plat/imx/imx8m/include/imx8m_psci.h
index c33d25e..7d14d11 100644
--- a/plat/imx/imx8m/include/imx8m_psci.h
+++ b/plat/imx/imx8m/include/imx8m_psci.h
@@ -19,5 +19,6 @@
 void imx_domain_suspend(const psci_power_state_t *target_state);
 void imx_domain_suspend_finish(const psci_power_state_t *target_state);
 void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state);
+int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie);
 
 #endif /* IMX8M_PSCI_H */
diff --git a/plat/mediatek/common/mtk_plat_common.c b/plat/mediatek/common/mtk_plat_common.c
index f57e435..142b5c9 100644
--- a/plat/mediatek/common/mtk_plat_common.c
+++ b/plat/mediatek/common/mtk_plat_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -139,9 +139,9 @@
 
 int32_t plat_get_soc_version(void)
 {
-	uint32_t manfid = (JEDEC_MTK_BKID << 24U) | (JEDEC_MTK_MFID << 16U);
+	uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_MTK_BKID, JEDEC_MTK_MFID);
 
-	return (int32_t)(manfid | (SOC_CHIP_ID & 0xFFFFU));
+	return (int32_t)(manfid | (SOC_CHIP_ID & SOC_ID_IMPL_DEF_MASK));
 }
 
 int32_t plat_get_soc_revision(void)
diff --git a/plat/nvidia/tegra/common/tegra_platform.c b/plat/nvidia/tegra/common/tegra_platform.c
index d45d988..3894b74 100644
--- a/plat/nvidia/tegra/common/tegra_platform.c
+++ b/plat/nvidia/tegra/common/tegra_platform.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -280,9 +280,9 @@
 int32_t plat_get_soc_version(void)
 {
 	uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK);
-	uint32_t manfid = (JEDEC_NVIDIA_BKID << 24) | (JEDEC_NVIDIA_MFID << 16);
+	uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_NVIDIA_BKID, JEDEC_NVIDIA_MFID);
 
-	return (int32_t)(manfid | (chip_id & 0xFFFF));
+	return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK));
 }
 
 /*
@@ -293,7 +293,8 @@
  */
 int32_t plat_get_soc_revision(void)
 {
-	return (int32_t)((tegra_get_chipid_major() << 8) | tegra_get_chipid_minor());
+	return (int32_t)(((tegra_get_chipid_major() << 8) | tegra_get_chipid_minor()) &
+			 SOC_ID_REV_MASK);
 }
 
 /*****************************************************************************
diff --git a/plat/nxp/common/plat_make_helper/plat_common_def.mk b/plat/nxp/common/plat_make_helper/plat_common_def.mk
new file mode 100644
index 0000000..86dacf8
--- /dev/null
+++ b/plat/nxp/common/plat_make_helper/plat_common_def.mk
@@ -0,0 +1,103 @@
+# Copyright 2020-2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Include build macros, for example: SET_NXP_MAKE_FLAG
+include plat/nxp/common/plat_make_helper/plat_build_macros.mk
+
+# Adding platform specific defines
+
+$(eval $(call add_define_val,BOARD,'"${BOARD}"'))
+
+ifeq (${POVDD_ENABLE},yes)
+$(eval $(call add_define,CONFIG_POVDD_ENABLE))
+endif
+
+ifneq (${FLASH_TYPE},)
+$(eval $(call add_define,CONFIG_${FLASH_TYPE}))
+endif
+
+ifneq (${XSPI_FLASH_SZ},)
+$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ}))
+endif
+
+ifneq (${QSPI_FLASH_SZ},)
+$(eval $(call add_define_val,NXP_QSPI_FLASH_SIZE,${QSPI_FLASH_SZ}))
+endif
+
+ifneq (${NOR_FLASH_SZ},)
+$(eval $(call add_define_val,NXP_NOR_FLASH_SIZE,${NOR_FLASH_SZ}))
+endif
+
+
+ifneq (${FSPI_ERASE_4K},)
+$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K}))
+endif
+
+ifneq (${NUM_OF_DDRC},)
+$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
+endif
+
+ifeq (${CONFIG_DDR_NODIMM},1)
+$(eval $(call add_define,CONFIG_DDR_NODIMM))
+DDRC_NUM_DIMM := 1
+endif
+
+ifneq (${DDRC_NUM_DIMM},)
+$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM}))
+endif
+
+ifneq (${DDRC_NUM_CS},)
+$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS}))
+endif
+
+ifeq (${DDR_ADDR_DEC},yes)
+$(eval $(call add_define,CONFIG_DDR_ADDR_DEC))
+endif
+
+ifeq (${DDR_ECC_EN},yes)
+$(eval $(call add_define,CONFIG_DDR_ECC_EN))
+endif
+
+ifeq (${CONFIG_STATIC_DDR},1)
+$(eval $(call add_define,CONFIG_STATIC_DDR))
+endif
+
+# Platform can control the base address for non-volatile storage.
+#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
+
+ifeq (${WARM_BOOT},yes)
+$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}'))
+endif
+
+# Selecting Boot Source for the TFA images.
+define add_boot_mode_define
+    ifeq ($(1),qspi)
+        $$(eval $$(call SET_NXP_MAKE_FLAG,QSPI_NEEDED,BL2))
+        $$(eval $$(call add_define,QSPI_BOOT))
+    else ifeq ($(1),sd)
+        $$(eval $$(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2))
+        $$(eval $$(call add_define,SD_BOOT))
+    else ifeq ($(1),emmc)
+        $$(eval $$(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2))
+        $$(eval $$(call add_define,EMMC_BOOT))
+    else ifeq ($(1),nor)
+        $$(eval $$(call SET_NXP_MAKE_FLAG,IFC_NOR_NEEDED,BL2))
+        $$(eval $$(call add_define,NOR_BOOT))
+    else ifeq ($(1),nand)
+        $$(eval $$(call SET_NXP_MAKE_FLAG,IFC_NAND_NEEDED,BL2))
+        $$(eval $$(call add_define,NAND_BOOT))
+    else ifeq ($(1),flexspi_nor)
+        $$(eval $$(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL2))
+        $$(eval $$(call add_define,FLEXSPI_NOR_BOOT))
+    else
+        $$(error $(PLAT) Cannot Support Boot Mode: $(BOOT_MODE))
+    endif
+endef
+
+ifneq (,$(findstring $(BOOT_MODE),$(SUPPORTED_BOOT_MODE)))
+    $(eval $(call add_boot_mode_define,$(strip $(BOOT_MODE))))
+else
+    $(error $(PLAT) Un-supported Boot Mode = $(BOOT_MODE))
+endif
diff --git a/plat/nxp/common/plat_make_helper/soc_common_def.mk b/plat/nxp/common/plat_make_helper/soc_common_def.mk
new file mode 100644
index 0000000..fdd7249
--- /dev/null
+++ b/plat/nxp/common/plat_make_helper/soc_common_def.mk
@@ -0,0 +1,114 @@
+# Copyright 2020-2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Adding SoC specific defines
+
+ifneq (${CACHE_LINE},)
+$(eval $(call add_define_val,PLATFORM_CACHE_LINE_SHIFT,${CACHE_LINE}))
+$(eval CACHE_WRITEBACK_GRANULE=$(shell echo $$((1 << $(CACHE_LINE)))))
+$(eval $(call add_define_val,CACHE_WRITEBACK_GRANULE,$(CACHE_WRITEBACK_GRANULE)))
+endif
+
+ifeq (${INTERCONNECT}, "CCI400")
+$(eval $(call add_define,NXP_HAS_${INTERCONNECT}))
+ICNNCT_ID := 0x420
+$(eval $(call add_define,ICNNCT_ID))
+endif
+
+ifeq (${INTERCONNECT}, "CCN508")
+$(eval $(call add_define,NXP_HAS_CCN508))
+endif
+
+ifneq (${CHASSIS},)
+$(eval $(call add_define,CONFIG_CHASSIS_${CHASSIS}))
+endif
+
+ifneq (${PLAT_DDR_PHY},)
+$(eval $(call add_define,NXP_DDR_${PLAT_DDR_PHY}))
+endif
+
+ifneq (${PHYS_SYS},)
+$(eval $(call add_define,CONFIG_PHYS_64BIT))
+endif
+
+ifneq (${CSF_HDR_SZ},)
+$(eval $(call add_define_val,CSF_HDR_SZ,${CSF_HDR_SZ}))
+endif
+
+ifneq (${OCRAM_START_ADDR},)
+$(eval $(call add_define_val,NXP_OCRAM_ADDR,${OCRAM_START_ADDR}))
+endif
+
+ifneq (${OCRAM_SIZE},)
+$(eval $(call add_define_val,NXP_OCRAM_SIZE,${OCRAM_SIZE}))
+endif
+
+ifneq (${NXP_ROM_RSVD},)
+$(eval $(call add_define_val,NXP_ROM_RSVD,${NXP_ROM_RSVD}))
+endif
+
+ifneq (${BL2_BASE},)
+$(eval $(call add_define_val,BL2_BASE,${BL2_BASE}))
+endif
+
+ifeq (${SEC_MEM_NON_COHERENT},yes)
+$(eval $(call add_define,SEC_MEM_NON_COHERENT))
+endif
+
+ifneq (${NXP_ESDHC_ENDIANNESS},)
+$(eval $(call add_define,NXP_ESDHC_${NXP_ESDHC_ENDIANNESS}))
+endif
+
+ifneq (${NXP_SFP_VER},)
+$(eval $(call add_define,NXP_SFP_VER_${NXP_SFP_VER}))
+endif
+
+ifneq (${NXP_SFP_ENDIANNESS},)
+$(eval $(call add_define,NXP_SFP_${NXP_SFP_ENDIANNESS}))
+endif
+
+ifneq (${NXP_GPIO_ENDIANNESS},)
+$(eval $(call add_define,NXP_GPIO_${NXP_GPIO_ENDIANNESS}))
+endif
+
+ifneq (${NXP_SNVS_ENDIANNESS},)
+$(eval $(call add_define,NXP_SNVS_${NXP_SNVS_ENDIANNESS}))
+endif
+
+ifneq (${NXP_GUR_ENDIANNESS},)
+$(eval $(call add_define,NXP_GUR_${NXP_GUR_ENDIANNESS}))
+endif
+
+ifneq (${NXP_FSPI_ENDIANNESS},)
+$(eval $(call add_define,NXP_FSPI_${NXP_FSPI_ENDIANNESS}))
+endif
+
+ifneq (${NXP_SEC_ENDIANNESS},)
+$(eval $(call add_define,NXP_SEC_${NXP_SEC_ENDIANNESS}))
+endif
+
+ifneq (${NXP_DDR_ENDIANNESS},)
+$(eval $(call add_define,NXP_DDR_${NXP_DDR_ENDIANNESS}))
+endif
+
+ifneq (${NXP_QSPI_ENDIANNESS},)
+$(eval $(call add_define,NXP_QSPI_${NXP_QSPI_ENDIANNESS}))
+endif
+
+ifneq (${NXP_SCFG_ENDIANNESS},)
+$(eval $(call add_define,NXP_SCFG_${NXP_SCFG_ENDIANNESS}))
+endif
+
+ifneq (${NXP_IFC_ENDIANNESS},)
+$(eval $(call add_define,NXP_IFC_${NXP_IFC_ENDIANNESS}))
+endif
+
+ifneq (${NXP_DDR_INTLV_256B},)
+$(eval $(call add_define,NXP_DDR_INTLV_256B))
+endif
+
+ifneq (${PLAT_XLAT_TABLES_DYNAMIC},)
+$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
+endif
diff --git a/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk b/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk
index 5b95222..226b22b 100644
--- a/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk
+++ b/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk
@@ -33,59 +33,19 @@
 # config is enabled for future use cases.
 FSPI_ERASE_4K	:= 0
 
- # Platform specific features.
+# Platform specific features.
 WARM_BOOT	:=	yes
 
- # Adding platform specific defines
-
-$(eval $(call add_define_val,BOARD,'"${BOARD}"'))
-
-ifeq (${POVDD_ENABLE},yes)
-$(eval $(call add_define,CONFIG_POVDD_ENABLE))
-endif
-
-ifneq (${FLASH_TYPE},)
-$(eval $(call add_define,CONFIG_${FLASH_TYPE}))
-endif
-
-ifneq (${XSPI_FLASH_SZ},)
-$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ}))
-endif
-
-ifneq (${FSPI_ERASE_4K},)
-$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K}))
-endif
-
-ifneq (${NUM_OF_DDRC},)
-$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
-endif
-
-ifneq (${DDRC_NUM_DIMM},)
-$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM}))
-endif
-
-ifneq (${DDRC_NUM_CS},)
-$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS}))
-endif
-
-ifeq (${DDR_ADDR_DEC},yes)
-$(eval $(call add_define,CONFIG_DDR_ADDR_DEC))
-endif
-
-ifeq (${DDR_ECC_EN},yes)
-$(eval $(call add_define,CONFIG_DDR_ECC_EN))
-endif
-
-# Platform can control the base address for non-volatile storage.
-#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
-
-ifeq (${WARM_BOOT},yes)
-$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}'))
-endif
-
- # Adding Platform files build files
+# Adding Platform files build files
 BL2_SOURCES	+=	${BOARD_PATH}/ddr_init.c\
 			${BOARD_PATH}/platform.c
 
- # Adding SoC build info
+SUPPORTED_BOOT_MODE	:=	flexspi_nor	\
+				sd		\
+				emmc
+
+# Adding platform board build info
+include plat/nxp/common/plat_make_helper/plat_common_def.mk
+
+# Adding SoC build info
 include plat/nxp/soc-lx2160a/soc.mk
diff --git a/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk b/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk
index e56fbf1..ffb5fad 100644
--- a/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk
+++ b/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk
@@ -36,56 +36,16 @@
  # Platform specific features.
 WARM_BOOT	:=	no
 
- # Adding platform specific defines
-
-$(eval $(call add_define_val,BOARD,'"${BOARD}"'))
-
-ifeq (${POVDD_ENABLE},yes)
-$(eval $(call add_define,CONFIG_POVDD_ENABLE))
-endif
-
-ifneq (${FLASH_TYPE},)
-$(eval $(call add_define,CONFIG_${FLASH_TYPE}))
-endif
-
-ifneq (${XSPI_FLASH_SZ},)
-$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ}))
-endif
-
-ifneq (${FSPI_ERASE_4K},)
-$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K}))
-endif
-
-ifneq (${NUM_OF_DDRC},)
-$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
-endif
-
-ifneq (${DDRC_NUM_DIMM},)
-$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM}))
-endif
-
-ifneq (${DDRC_NUM_CS},)
-$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS}))
-endif
-
-ifeq (${DDR_ADDR_DEC},yes)
-$(eval $(call add_define,CONFIG_DDR_ADDR_DEC))
-endif
-
-ifeq (${DDR_ECC_EN},yes)
-$(eval $(call add_define,CONFIG_DDR_ECC_EN))
-endif
-
-# Platform can control the base address for non-volatile storage.
-#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
-
-ifeq (${WARM_BOOT},yes)
-$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}'))
-endif
-
  # Adding Platform files build files
 BL2_SOURCES	+=	${BOARD_PATH}/ddr_init.c\
 			${BOARD_PATH}/platform.c
 
+SUPPORTED_BOOT_MODE	:=	flexspi_nor	\
+				sd		\
+				emmc
+
+# Adding platform board build info
+include plat/nxp/common/plat_make_helper/plat_common_def.mk
+
  # Adding SoC build info
 include plat/nxp/soc-lx2160a/soc.mk
diff --git a/plat/nxp/soc-lx2160a/lx2162aqds/platform.mk b/plat/nxp/soc-lx2160a/lx2162aqds/platform.mk
index fbdcd83..2b4712c 100644
--- a/plat/nxp/soc-lx2160a/lx2162aqds/platform.mk
+++ b/plat/nxp/soc-lx2160a/lx2162aqds/platform.mk
@@ -25,7 +25,7 @@
 ERRATA_DDR_A050450	:= 1
 
 
- # On-Board Flash Details
+# On-Board Flash Details
 FLASH_TYPE	:=	MT35XU512A
 XSPI_FLASH_SZ	:=	0x10000000
 NXP_XSPI_NOR_UNIT_SIZE		:=	0x20000
@@ -34,59 +34,19 @@
 # config is enabled for future use cases.
 FSPI_ERASE_4K	:= 0
 
- # Platform specific features.
+# Platform specific features.
 WARM_BOOT	:=	yes
 
- # Adding platform specific defines
-
-$(eval $(call add_define_val,BOARD,'"${BOARD}"'))
-
-ifeq (${POVDD_ENABLE},yes)
-$(eval $(call add_define,CONFIG_POVDD_ENABLE))
-endif
-
-ifneq (${FLASH_TYPE},)
-$(eval $(call add_define,CONFIG_${FLASH_TYPE}))
-endif
-
-ifneq (${XSPI_FLASH_SZ},)
-$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ}))
-endif
-
-ifneq (${FSPI_ERASE_4K},)
-$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K}))
-endif
-
-ifneq (${NUM_OF_DDRC},)
-$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
-endif
-
-ifneq (${DDRC_NUM_DIMM},)
-$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM}))
-endif
-
-ifneq (${DDRC_NUM_CS},)
-$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS}))
-endif
-
-ifeq (${DDR_ADDR_DEC},yes)
-$(eval $(call add_define,CONFIG_DDR_ADDR_DEC))
-endif
-
-ifeq (${DDR_ECC_EN},yes)
-$(eval $(call add_define,CONFIG_DDR_ECC_EN))
-endif
-
-# Platform can control the base address for non-volatile storage.
-#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
-
-ifeq (${WARM_BOOT},yes)
-$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}'))
-endif
-
- # Adding Platform files build files
+# Adding Platform files build files
 BL2_SOURCES	+=	${BOARD_PATH}/ddr_init.c\
 			${BOARD_PATH}/platform.c
 
- # Adding SoC build info
+SUPPORTED_BOOT_MODE	:=	flexspi_nor	\
+				sd		\
+				emmc
+
+# Adding platform board build info
+include plat/nxp/common/plat_make_helper/plat_common_def.mk
+
+# Adding SoC build info
 include plat/nxp/soc-lx2160a/soc.mk
diff --git a/plat/rpi/rpi4/include/rpi_hw.h b/plat/rpi/rpi4/include/rpi_hw.h
index 7185106..0430d46 100644
--- a/plat/rpi/rpi4/include/rpi_hw.h
+++ b/plat/rpi/rpi4/include/rpi_hw.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,14 +13,16 @@
  * Peripherals
  */
 
-#define RPI_IO_BASE			ULL(0xFE000000)
-#define RPI_IO_SIZE			ULL(0x02000000)
+#define RPI_IO_BASE			ULL(0xFC000000)
+#define RPI_IO_SIZE			ULL(0x04000000)
+
+#define RPI_LEGACY_BASE			(ULL(0x02000000) + RPI_IO_BASE)
 
 /*
  * ARM <-> VideoCore mailboxes
  */
 #define RPI3_MBOX_OFFSET		ULL(0x0000B880)
-#define RPI3_MBOX_BASE			(RPI_IO_BASE + RPI3_MBOX_OFFSET)
+#define RPI3_MBOX_BASE			(RPI_LEGACY_BASE + RPI3_MBOX_OFFSET)
 /* VideoCore -> ARM */
 #define RPI3_MBOX0_READ_OFFSET		ULL(0x00000000)
 #define RPI3_MBOX0_PEEK_OFFSET		ULL(0x00000010)
@@ -41,7 +43,7 @@
  * Power management, reset controller, watchdog.
  */
 #define RPI3_IO_PM_OFFSET		ULL(0x00100000)
-#define RPI3_PM_BASE			(RPI_IO_BASE + RPI3_IO_PM_OFFSET)
+#define RPI3_PM_BASE			(RPI_LEGACY_BASE + RPI3_IO_PM_OFFSET)
 /* Registers on top of RPI3_PM_BASE. */
 #define RPI3_PM_RSTC_OFFSET		ULL(0x0000001C)
 #define RPI3_PM_RSTS_OFFSET		ULL(0x00000020)
@@ -62,7 +64,7 @@
  * Hardware random number generator.
  */
 #define RPI3_IO_RNG_OFFSET		ULL(0x00104000)
-#define RPI3_RNG_BASE			(RPI_IO_BASE + RPI3_IO_RNG_OFFSET)
+#define RPI3_RNG_BASE			(RPI_LEGACY_BASE + RPI3_IO_RNG_OFFSET)
 #define RPI3_RNG_CTRL_OFFSET		ULL(0x00000000)
 #define RPI3_RNG_STATUS_OFFSET		ULL(0x00000004)
 #define RPI3_RNG_DATA_OFFSET		ULL(0x00000008)
@@ -82,22 +84,22 @@
  * There is also a PL011 UART, multiplexed to the same pins.
  */
 #define RPI4_IO_MINI_UART_OFFSET	ULL(0x00215040)
-#define RPI4_MINI_UART_BASE		(RPI_IO_BASE + RPI4_IO_MINI_UART_OFFSET)
+#define RPI4_MINI_UART_BASE		(RPI_LEGACY_BASE + RPI4_IO_MINI_UART_OFFSET)
 #define RPI4_IO_PL011_UART_OFFSET	ULL(0x00201000)
-#define RPI4_PL011_UART_BASE		(RPI_IO_BASE + RPI4_IO_PL011_UART_OFFSET)
+#define RPI4_PL011_UART_BASE		(RPI_LEGACY_BASE + RPI4_IO_PL011_UART_OFFSET)
 #define RPI4_PL011_UART_CLOCK		ULL(48000000)
 
 /*
  * GPIO controller
  */
 #define RPI3_IO_GPIO_OFFSET		ULL(0x00200000)
-#define RPI3_GPIO_BASE			(RPI_IO_BASE + RPI3_IO_GPIO_OFFSET)
+#define RPI3_GPIO_BASE			(RPI_LEGACY_BASE + RPI3_IO_GPIO_OFFSET)
 
 /*
  * SDHost controller
  */
 #define RPI3_IO_SDHOST_OFFSET           ULL(0x00202000)
-#define RPI3_SDHOST_BASE                (RPI_IO_BASE + RPI3_IO_SDHOST_OFFSET)
+#define RPI3_SDHOST_BASE                (RPI_LEGACY_BASE + RPI3_IO_SDHOST_OFFSET)
 
 /*
  * GIC interrupt controller
diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h
index feeb4a7..42d3487 100644
--- a/plat/st/common/include/stm32mp_common.h
+++ b/plat/st/common/include/stm32mp_common.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,6 +11,9 @@
 
 #include <platform_def.h>
 
+#define JEDEC_ST_BKID U(0x0)
+#define JEDEC_ST_MFID U(0x20)
+
 /* Functions to save and get boot context address given by ROM code */
 void stm32mp_save_boot_ctx_address(uintptr_t address);
 uintptr_t stm32mp_get_boot_ctx_address(void);
@@ -64,6 +67,15 @@
 /* Return node offset for target GPIO bank ID @bank or a FDT error code */
 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank);
 
+/* Get the chip revision */
+uint32_t stm32mp_get_chip_version(void);
+/* Get the chip device ID */
+uint32_t stm32mp_get_chip_dev_id(void);
+
+/* Get SOC name */
+#define STM32_SOC_NAME_SIZE 20
+void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]);
+
 /* Print CPU information */
 void stm32mp_print_cpuinfo(void);
 
diff --git a/plat/st/common/include/stm32mp_dt.h b/plat/st/common/include/stm32mp_dt.h
index e3b4e59..299c0b1 100644
--- a/plat/st/common/include/stm32mp_dt.h
+++ b/plat/st/common/include/stm32mp_dt.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,6 +9,7 @@
 #define STM32MP_DT_H
 
 #include <stdbool.h>
+#include <stdint.h>
 
 #define DT_DISABLED		U(0)
 #define DT_NON_SECURE		U(1)
@@ -25,7 +26,7 @@
 /*******************************************************************************
  * Function and variable prototypes
  ******************************************************************************/
-int dt_open_and_check(void);
+int dt_open_and_check(uintptr_t dt_addr);
 int fdt_get_address(void **fdt_addr);
 bool fdt_check_node(int node);
 uint8_t fdt_get_status(int node);
diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c
index 89d8078..d3de1e1 100644
--- a/plat/st/common/stm32mp_common.c
+++ b/plat/st/common/stm32mp_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,8 +12,10 @@
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <drivers/st/stm32mp_clkfunc.h>
+#include <lib/smccc.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #include <plat/common/platform.h>
+#include <services/arm_arch_svc.h>
 
 uintptr_t plat_get_ns_image_entrypoint(void)
 {
@@ -111,3 +113,36 @@
 	return  mmap_remove_dynamic_region(STM32MP_DDR_BASE,
 					   STM32MP_DDR_MAX_SIZE);
 }
+
+/*****************************************************************************
+ * plat_is_smccc_feature_available() - This function checks whether SMCCC
+ *                                     feature is availabile for platform.
+ * @fid: SMCCC function id
+ *
+ * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
+ * SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
+ *****************************************************************************/
+int32_t plat_is_smccc_feature_available(u_register_t fid)
+{
+	switch (fid) {
+	case SMCCC_ARCH_SOC_ID:
+		return SMC_ARCH_CALL_SUCCESS;
+	default:
+		return SMC_ARCH_CALL_NOT_SUPPORTED;
+	}
+}
+
+/* Get SOC version */
+int32_t plat_get_soc_version(void)
+{
+	uint32_t chip_id = stm32mp_get_chip_dev_id();
+	uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_ST_BKID, JEDEC_ST_MFID);
+
+	return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK));
+}
+
+/* Get SOC revision */
+int32_t plat_get_soc_revision(void)
+{
+	return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK);
+}
diff --git a/plat/st/common/stm32mp_dt.c b/plat/st/common/stm32mp_dt.c
index 4f130ce..6465c10 100644
--- a/plat/st/common/stm32mp_dt.c
+++ b/plat/st/common/stm32mp_dt.c
@@ -19,20 +19,19 @@
 
 #include <stm32mp_dt.h>
 
-static int fdt_checked;
-
-static void *fdt = (void *)(uintptr_t)STM32MP_DTB_BASE;
+static void *fdt;
 
 /*******************************************************************************
  * This function checks device tree file with its header.
  * Returns 0 on success and a negative FDT error code on failure.
  ******************************************************************************/
-int dt_open_and_check(void)
+int dt_open_and_check(uintptr_t dt_addr)
 {
-	int ret = fdt_check_header(fdt);
+	int ret;
 
+	ret = fdt_check_header((void *)dt_addr);
 	if (ret == 0) {
-		fdt_checked = 1;
+		fdt = (void *)dt_addr;
 	}
 
 	return ret;
@@ -45,11 +44,13 @@
  ******************************************************************************/
 int fdt_get_address(void **fdt_addr)
 {
-	if (fdt_checked == 1) {
-		*fdt_addr = fdt;
+	if (fdt == NULL) {
+		return 0;
 	}
 
-	return fdt_checked;
+	*fdt_addr = fdt;
+
+	return 1;
 }
 
 /*******************************************************************************
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 0e95f49..91073b8 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -196,7 +196,7 @@
 
 	configure_mmu();
 
-	if (dt_open_and_check() < 0) {
+	if (dt_open_and_check(STM32MP_DTB_BASE) < 0) {
 		panic();
 	}
 
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 128dbc4..e6645e0 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -44,11 +44,6 @@
 STM32MP_SPI_NOR		?=	0
 STM32MP_EMMC_BOOT	?=	0
 
-ifeq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC} ${STM32MP_RAW_NAND} \
-	${STM32MP_SPI_NAND} ${STM32MP_SPI_NOR}),)
-$(error "No boot device driver is enabled")
-endif
-
 # Device tree
 DTB_FILE_NAME		?=	stm32mp157c-ev1.dtb
 FDT_SOURCES		:=	$(addprefix fdts/, $(patsubst %.dtb,%.dts,$(DTB_FILE_NAME)))
@@ -199,13 +194,25 @@
 endif
 
 # Compilation rules
-.PHONY: check_dtc_version stm32image clean_stm32image
+.PHONY: check_dtc_version stm32image clean_stm32image check_boot_device
 .SUFFIXES:
 
 all: check_dtc_version stm32image ${STM32_TF_STM32}
 
 distclean realclean clean: clean_stm32image
 
+bl2: check_boot_device
+
+check_boot_device:
+	@if [ ${STM32MP_EMMC} != 1 ] && \
+	    [ ${STM32MP_SDMMC} != 1 ] && \
+	    [ ${STM32MP_RAW_NAND} != 1 ] && \
+	    [ ${STM32MP_SPI_NAND} != 1 ] && \
+	    [ ${STM32MP_SPI_NOR} != 1 ]; then \
+		echo "No boot device driver is enabled"; \
+		false; \
+	fi
+
 stm32image: ${STM32IMAGE}
 
 ${STM32IMAGE}: ${STM32IMAGE_SRC}
diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c
index 9b8c3ea..334f914a 100644
--- a/plat/st/stm32mp1/sp_min/sp_min_setup.c
+++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c
@@ -146,7 +146,7 @@
 		bl_params = bl_params->next_params_info;
 	}
 
-	if (dt_open_and_check() < 0) {
+	if (dt_open_and_check(STM32MP_DTB_BASE) < 0) {
 		panic();
 	}
 
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 9e5bfdc..155d63d 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -31,6 +31,8 @@
 /*******************************************************************************
  * CHIP ID
  ******************************************************************************/
+#define STM32MP1_CHIP_ID	U(0x500)
+
 #define STM32MP157C_PART_NB	U(0x05000000)
 #define STM32MP157A_PART_NB	U(0x05000001)
 #define STM32MP153C_PART_NB	U(0x05000024)
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index bc77ee3..1af0075 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -153,63 +153,70 @@
 	}
 }
 
-static int get_part_number(uint32_t *part_nb)
+uint32_t stm32mp_get_chip_version(void)
 {
-	uint32_t part_number;
+	uint32_t version = 0U;
+
+	if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) {
+		INFO("Cannot get CPU version, debug disabled\n");
+		return 0U;
+	}
+
+	return version;
+}
+
+uint32_t stm32mp_get_chip_dev_id(void)
+{
 	uint32_t dev_id;
 
-	assert(part_nb != NULL);
-
 	if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) {
-		return -1;
+		INFO("Use default chip ID, debug disabled\n");
+		dev_id = STM32MP1_CHIP_ID;
+	}
+
+	return dev_id;
+}
+
+static uint32_t get_part_number(void)
+{
+	static uint32_t part_number;
+
+	if (part_number != 0U) {
+		return part_number;
 	}
 
 	if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) {
-		ERROR("BSEC: PART_NUMBER_OTP Error\n");
-		return -1;
+		panic();
 	}
 
 	part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >>
 		PART_NUMBER_OTP_PART_SHIFT;
 
-	*part_nb = part_number | (dev_id << 16);
+	part_number |= stm32mp_get_chip_dev_id() << 16;
 
-	return 0;
+	return part_number;
 }
 
-static int get_cpu_package(uint32_t *cpu_package)
+static uint32_t get_cpu_package(void)
 {
 	uint32_t package;
 
-	assert(cpu_package != NULL);
-
 	if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) {
-		ERROR("BSEC: PACKAGE_OTP Error\n");
-		return -1;
+		panic();
 	}
 
-	*cpu_package = (package & PACKAGE_OTP_PKG_MASK) >>
+	package = (package & PACKAGE_OTP_PKG_MASK) >>
 		PACKAGE_OTP_PKG_SHIFT;
 
-	return 0;
+	return package;
 }
 
-void stm32mp_print_cpuinfo(void)
+void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE])
 {
-	const char *cpu_s, *cpu_r, *pkg;
-	uint32_t part_number;
-	uint32_t cpu_package;
-	uint32_t chip_dev_id;
-	int ret;
+	char *cpu_s, *cpu_r, *pkg;
 
 	/* MPUs Part Numbers */
-	ret = get_part_number(&part_number);
-	if (ret < 0) {
-		WARN("Cannot get part number\n");
-		return;
-	}
-
-	switch (part_number) {
+	switch (get_part_number()) {
 	case STM32MP157C_PART_NB:
 		cpu_s = "157C";
 		break;
@@ -252,13 +259,7 @@
 	}
 
 	/* Package */
-	ret = get_cpu_package(&cpu_package);
-	if (ret < 0) {
-		WARN("Cannot get CPU package\n");
-		return;
-	}
-
-	switch (cpu_package) {
+	switch (get_cpu_package()) {
 	case PKG_AA_LFBGA448:
 		pkg = "AA";
 		break;
@@ -277,13 +278,7 @@
 	}
 
 	/* REVISION */
-	ret = stm32mp1_dbgmcu_get_chip_version(&chip_dev_id);
-	if (ret < 0) {
-		WARN("Cannot get CPU version\n");
-		return;
-	}
-
-	switch (chip_dev_id) {
+	switch (stm32mp_get_chip_version()) {
 	case STM32MP1_REV_B:
 		cpu_r = "B";
 		break;
@@ -295,7 +290,16 @@
 		break;
 	}
 
-	NOTICE("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r);
+	snprintf(name, STM32_SOC_NAME_SIZE,
+		 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r);
+}
+
+void stm32mp_print_cpuinfo(void)
+{
+	char name[STM32_SOC_NAME_SIZE];
+
+	stm32mp_get_soc_name(name);
+	NOTICE("CPU: %s\n", name);
 }
 
 void stm32mp_print_boardinfo(void)
@@ -349,20 +353,12 @@
 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */
 bool stm32mp_is_single_core(void)
 {
-	uint32_t part_number;
-
-	if (get_part_number(&part_number) < 0) {
-		ERROR("Invalid part number, assume single core chip");
-		return true;
-	}
-
-	switch (part_number) {
+	switch (get_part_number()) {
 	case STM32MP151A_PART_NB:
 	case STM32MP151C_PART_NB:
 	case STM32MP151D_PART_NB:
 	case STM32MP151F_PART_NB:
 		return true;
-
 	default:
 		return false;
 	}
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index ec433ff..fae73cf 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -148,11 +148,6 @@
 		.id = 0x40,
 		.name = "XCZU11EG",
 	},
-	{ /* For testing purpose only */
-		.id = 0x50,
-		.ver = 0x2c,
-		.name = "XCZU15CG",
-	},
 	{
 		.id = 0x50,
 		.name = "XCZU15EG",
@@ -334,9 +329,10 @@
 		break;
 	}
 
-	NOTICE("TF-A running on %s/%s v%d/RTL%d.%d at 0x%x\n",
-	       zynqmp_print_silicon_idcode(), label, zynqmp_get_ps_ver(),
-	       (rtl & 0xf0) >> 4, rtl & 0xf, BL31_BASE);
+	NOTICE("TF-A running on %s/%s at 0x%x\n",
+	       zynqmp_print_silicon_idcode(), label, BL31_BASE);
+	VERBOSE("TF-A running on v%d/RTL%d.%d\n",
+	       zynqmp_get_ps_ver(), (rtl & 0xf0) >> 4, rtl & 0xf);
 }
 #else
 static inline void zynqmp_print_platform_name(void) { }
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index 4a09b4b..bbe297f 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -123,25 +123,6 @@
 	}
 }
 
-/* Enable the test setup */
-#ifndef ZYNQMP_TESTING
-static void zynqmp_testing_setup(void) { }
-#else
-static void zynqmp_testing_setup(void)
-{
-	uint32_t actlr_el3, actlr_el2;
-
-	/* Enable CPU ACTLR AND L2ACTLR RW access from non-secure world */
-	actlr_el3 = read_actlr_el3();
-	actlr_el2 = read_actlr_el2();
-
-	actlr_el3 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT;
-	actlr_el2 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT;
-	write_actlr_el3(actlr_el3);
-	write_actlr_el2(actlr_el2);
-}
-#endif
-
 #if ZYNQMP_WDT_RESTART
 static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3];
 
@@ -183,7 +164,6 @@
 	/* Initialize the gic cpu and distributor interfaces */
 	plat_arm_gic_driver_init();
 	plat_arm_gic_init();
-	zynqmp_testing_setup();
 }
 
 void bl31_plat_runtime_setup(void)
diff --git a/plat/xilinx/zynqmp/plat_psci.c b/plat/xilinx/zynqmp/plat_psci.c
index f579f79..f78b88c 100644
--- a/plat/xilinx/zynqmp/plat_psci.c
+++ b/plat/xilinx/zynqmp/plat_psci.c
@@ -179,14 +179,6 @@
 	return PSCI_E_SUCCESS;
 }
 
-int zynqmp_validate_ns_entrypoint(unsigned long ns_entrypoint)
-{
-	VERBOSE("%s: ns_entrypoint: 0x%lx\n", __func__, ns_entrypoint);
-
-	/* FIXME: Actually validate */
-	return PSCI_E_SUCCESS;
-}
-
 void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state)
 {
 	req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
@@ -206,7 +198,6 @@
 	.system_off			= zynqmp_system_off,
 	.system_reset			= zynqmp_system_reset,
 	.validate_power_state		= zynqmp_validate_power_state,
-	.validate_ns_entrypoint		= zynqmp_validate_ns_entrypoint,
 	.get_sys_suspend_power_state	= zynqmp_get_sys_suspend_power_state,
 };