)]}' { "commit": "308dce40679f63db504cd3d746a0c37a2a05f473", "tree": "00b17593c2ac0038deb2480731083ffea3e49dfa", "parents": [ "1bbe2135c3123bd732c846f61361b11d8623072b" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Jan 24 05:45:15 2022 -0800" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Wed Apr 06 08:14:39 2022 +0100" }, "message": "feat(gic600ae_fmu): introduce support for RAS error handling\n\nThe GIC-600AE uses a range of RAS features for all RAMs, which include\nSECDED, ECC, and Scrub, software and bus error reporting. The GIC makes\nall necessary information available to software through Armv8.2 RAS\narchitecture compliant register space.\n\nThis patch introduces support to probe the FMU_ERRGSR register to find\nthe right error record. Once the correct record is identified, the\n\"handler\" function queries the FMU_ERR\u003cm\u003eSTATUS register to further\nidentify the block ID, safety mechanism and the architecturally defined\nprimary error code. The description of the error is displayed on the\nconsole to simplify debug.\n\nChange-Id: I7e543664b74457afee2da250549f4c3d9beb1a03\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\n", "tree_diff": [ { "type": "modify", "old_id": "13979fa4d6471ae7aeae084b6de21908bad53711", "old_mode": 33188, "old_path": "drivers/arm/gic/v3/gic600ae_fmu.c", "new_id": "2233bbf93ac7e355fa3c4257839220b7aaeaf160", "new_mode": 33188, "new_path": "drivers/arm/gic/v3/gic600ae_fmu.c" }, { "type": "modify", "old_id": "691ffc7b75d53bbafa9332bde939857953fc6446", "old_mode": 33188, "old_path": "include/drivers/arm/gic600ae_fmu.h", "new_id": "f7dcbb8a2ec76b97ff25d75c4f95ed91e72c564e", "new_mode": 33188, "new_path": "include/drivers/arm/gic600ae_fmu.h" } ] }