Workaround for Neoverse N1 erratum 1257314
Neoverse N1 erratum 1257314 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR3_EL1 system register, which prevents parallel
execution of divide and square root instructions.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index ee8da17..14dfe95 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -243,6 +243,9 @@
- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1
CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
+- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1
+ CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
+
- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.