)]}' { "commit": "337ff4f1dd6604738d79fd3fa275ae74d74256b2", "tree": "dc1dfa97f8e30ff7c51bf3719701eab311248b4f", "parents": [ "4f2c4ecfb087dd32b277000dc1578837dee1fd71" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue Oct 04 13:41:32 2022 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Oct 05 10:17:55 2022 +0100" }, "message": "fix(qemu): enable SVE and SME\n\nStarting with QEMU v3.1.0 (Dec 2018), QEMU\u0027s TCG emulation engine supports\nthe SVE architecture extension. In QEMU v7.1.0 (Aug 2022) it also gained\nSME support.\n\nAs it stands today, running TF-A under QEMU with \"-cpu max\" makes Linux\nhang, because SME and SVE accesses trap to EL3, but are never handled\nthere. This is because the Linux kernel sees the SVE or SME feature bits,\nand assumes firmware has enabled the feature for lower exception levels.\nThis requirement is described in the Linux kernel booting protocol.\n\nEnable those features in the TF-A build, so that BL31 does the proper\nEL3 setup to make the feature usable in non-secure world.\nWe check the actual feature bits before accessing SVE or SME registers,\nso this is safe even for older QEMU version or when not running with\n-cpu max. As SVE and SME are AArch64 features only, do not enable them\nwhen building for AArch32.\n\nChange-Id: I5b718eb298a0bbcf36244479e8d42e54a2faca61\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n", "tree_diff": [ { "type": "modify", "old_id": "e0b52710e453b9503f15f8af674fb3eb1b70e1fc", "old_mode": 33188, "old_path": "plat/qemu/qemu/platform.mk", "new_id": "6becc32fad5c1c80d36fc89bfd6784f3f78c6bb5", "new_mode": 33188, "new_path": "plat/qemu/qemu/platform.mk" } ] }