intel: Refactor reset manager driver
Refactor reset manager into intel common platform directory as it can be
shared by both Stratix 10 and Agilex. Register address and field is now
referred through macros.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Id6d50f2a2f5a6bd8d6746b84602ac17ec7f6c07a
diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c
index d160279..a27680c 100644
--- a/plat/intel/soc/agilex/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex/bl2_plat_setup.c
@@ -18,13 +18,13 @@
#include "agilex_clock_manager.h"
#include "agilex_memory_controller.h"
#include "agilex_pinmux.h"
-#include "agilex_reset_manager.h"
#include "agilex_system_manager.h"
#include "ccu/ncore_ccu.h"
#include "qspi/cadence_qspi.h"
#include "socfpga_handoff.h"
#include "socfpga_mailbox.h"
#include "socfpga_private.h"
+#include "socfpga_reset_manager.h"
#include "wdt/watchdog.h"
diff --git a/plat/intel/soc/agilex/include/agilex_reset_manager.h b/plat/intel/soc/agilex/include/agilex_reset_manager.h
deleted file mode 100644
index 9c9c884..0000000
--- a/plat/intel/soc/agilex/include/agilex_reset_manager.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef AGX_RESETMANAGER_H
-#define AGX_RESETMANAGER_H
-
-#define AGX_RSTMGR_HDSKEN 0xffd11010
-#define AGX_RSTMGR_PER0MODRST 0xffd11024
-#define AGX_RSTMGR_PER1MODRST 0xffd11028
-#define AGX_RSTMGR_BRGMODRST 0xffd1102c
-
-#define AGX_RSTMGR_PER0MODRST_EMAC0 0x00000001
-#define AGX_RSTMGR_PER0MODRST_EMAC1 0x00000002
-#define AGX_RSTMGR_PER0MODRST_EMAC2 0x00000004
-#define AGX_RSTMGR_PER0MODRST_USB0 0x00000008
-#define AGX_RSTMGR_PER0MODRST_USB1 0x00000010
-#define AGX_RSTMGR_PER0MODRST_NAND 0x00000020
-#define AGX_RSTMGR_PER0MODRST_SDMMC 0x00000080
-#define AGX_RSTMGR_PER0MODRST_EMAC0OCP 0x00000100
-#define AGX_RSTMGR_PER0MODRST_EMAC1OCP 0x00000200
-#define AGX_RSTMGR_PER0MODRST_EMAC2OCP 0x00000400
-#define AGX_RSTMGR_PER0MODRST_USB0OCP 0x00000800
-#define AGX_RSTMGR_PER0MODRST_USB1OCP 0x00001000
-#define AGX_RSTMGR_PER0MODRST_NANDOCP 0x00002000
-#define AGX_RSTMGR_PER0MODRST_SDMMCOCP 0x00008000
-#define AGX_RSTMGR_PER0MODRST_DMA 0x00010000
-#define AGX_RSTMGR_PER0MODRST_SPIM0 0x00020000
-#define AGX_RSTMGR_PER0MODRST_SPIM1 0x00040000
-#define AGX_RSTMGR_PER0MODRST_SPIS0 0x00080000
-#define AGX_RSTMGR_PER0MODRST_SPIS1 0x00100000
-#define AGX_RSTMGR_PER0MODRST_DMAOCP 0x00200000
-#define AGX_RSTMGR_PER0MODRST_EMACPTP 0x00400000
-#define AGX_RSTMGR_PER0MODRST_DMAIF0 0x01000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF1 0x02000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF2 0x04000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF3 0x08000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF4 0x10000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF5 0x20000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF6 0x40000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF7 0x80000000
-
-#define AGX_RSTMGR_PER1MODRST_WATCHDOG0 0x1
-#define AGX_RSTMGR_PER1MODRST_WATCHDOG1 0x2
-#define AGX_RSTMGR_PER1MODRST_WATCHDOG2 0x4
-#define AGX_RSTMGR_PER1MODRST_WATCHDOG3 0x8
-#define AGX_RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010
-#define AGX_RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020
-#define AGX_RSTMGR_PER1MODRST_SPTIMER0 0x00000040
-#define AGX_RSTMGR_PER1MODRST_SPTIMER1 0x00000080
-#define AGX_RSTMGR_PER1MODRST_I2C0 0x00000100
-#define AGX_RSTMGR_PER1MODRST_I2C1 0x00000200
-#define AGX_RSTMGR_PER1MODRST_I2C2 0x00000400
-#define AGX_RSTMGR_PER1MODRST_I2C3 0x00000800
-#define AGX_RSTMGR_PER1MODRST_I2C4 0x00001000
-#define AGX_RSTMGR_PER1MODRST_UART0 0x00010000
-#define AGX_RSTMGR_PER1MODRST_UART1 0x00020000
-#define AGX_RSTMGR_PER1MODRST_GPIO0 0x01000000
-#define AGX_RSTMGR_PER1MODRST_GPIO1 0x02000000
-
-#define AGX_RSTMGR_HDSKEN_FPGAHSEN 0x00000004
-#define AGX_RSTMGR_HDSKEN_ETRSTALLEN 0x00000008
-#define AGX_RSTMGR_HDSKEN_L2FLUSHEN 0x00000100
-#define AGX_RSTMGR_HDSKEN_L3NOC_DBG 0x00010000
-#define AGX_RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000
-#define AGX_RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001
-
-#define AGX_RSTMGR_BRGMODRST_SOC2FPGA 0x1
-#define AGX_RSTMGR_BRGMODRST_LWHPS2FPGA 0x2
-#define AGX_RSTMGR_BRGMODRST_FPGA2SOC 0x4
-#define AGX_RSTMGR_BRGMODRST_MPFE 0x40
-
-void deassert_peripheral_reset(void);
-void config_hps_hs_before_warm_reset(void);
-int socfpga_bridges_enable(void);
-int socfpga_bridges_disable(void);
-
-#endif
-
diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h
index a346cb5..3867503 100644
--- a/plat/intel/soc/agilex/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -15,9 +15,7 @@
/* Register Mapping */
#define SOCFPGA_MMC_REG_BASE 0xff808000
-
-#define SOCFPGA_RSTMGR_OFST 0xffd11000
-#define SOCFPGA_RSTMGR_MPUMODRST_OFST 0xffd11020
+#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000
#endif /* PLAT_SOCFPGA_DEF_H */
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk
index ef02a8d..c4904be 100644
--- a/plat/intel/soc/agilex/platform.mk
+++ b/plat/intel/soc/agilex/platform.mk
@@ -38,7 +38,6 @@
plat/intel/soc/agilex/soc/agilex_clock_manager.c \
plat/intel/soc/agilex/soc/agilex_memory_controller.c \
plat/intel/soc/agilex/soc/agilex_pinmux.c \
- plat/intel/soc/agilex/soc/agilex_reset_manager.c \
plat/intel/soc/agilex/soc/agilex_system_manager.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/common/socfpga_delay_timer.c \
@@ -46,6 +45,7 @@
plat/intel/soc/common/socfpga_storage.c \
plat/intel/soc/common/soc/socfpga_handoff.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
+ plat/intel/soc/common/soc/socfpga_reset_manager.c \
plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
plat/intel/soc/common/drivers/wdt/watchdog.c \
plat/intel/soc/common/drivers/ccu/ncore_ccu.c
diff --git a/plat/intel/soc/agilex/soc/agilex_reset_manager.c b/plat/intel/soc/agilex/soc/agilex_reset_manager.c
deleted file mode 100644
index 1224a90..0000000
--- a/plat/intel/soc/agilex/soc/agilex_reset_manager.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <errno.h>
-#include <lib/mmio.h>
-
-#include "agilex_reset_manager.h"
-#include "agilex_system_manager.h"
-#include "socfpga_mailbox.h"
-
-void deassert_peripheral_reset(void)
-{
- mmio_clrbits_32(AGX_RSTMGR_PER1MODRST,
- AGX_RSTMGR_PER1MODRST_WATCHDOG0 |
- AGX_RSTMGR_PER1MODRST_WATCHDOG1 |
- AGX_RSTMGR_PER1MODRST_WATCHDOG2 |
- AGX_RSTMGR_PER1MODRST_WATCHDOG3 |
- AGX_RSTMGR_PER1MODRST_L4SYSTIMER0 |
- AGX_RSTMGR_PER1MODRST_L4SYSTIMER1 |
- AGX_RSTMGR_PER1MODRST_SPTIMER0 |
- AGX_RSTMGR_PER1MODRST_SPTIMER1 |
- AGX_RSTMGR_PER1MODRST_I2C0 |
- AGX_RSTMGR_PER1MODRST_I2C1 |
- AGX_RSTMGR_PER1MODRST_I2C2 |
- AGX_RSTMGR_PER1MODRST_I2C3 |
- AGX_RSTMGR_PER1MODRST_I2C4 |
- AGX_RSTMGR_PER1MODRST_UART0 |
- AGX_RSTMGR_PER1MODRST_UART1 |
- AGX_RSTMGR_PER1MODRST_GPIO0 |
- AGX_RSTMGR_PER1MODRST_GPIO1);
-
- mmio_clrbits_32(AGX_RSTMGR_PER0MODRST,
- AGX_RSTMGR_PER0MODRST_EMAC0OCP |
- AGX_RSTMGR_PER0MODRST_EMAC1OCP |
- AGX_RSTMGR_PER0MODRST_EMAC2OCP |
- AGX_RSTMGR_PER0MODRST_USB0OCP |
- AGX_RSTMGR_PER0MODRST_USB1OCP |
- AGX_RSTMGR_PER0MODRST_NANDOCP |
- AGX_RSTMGR_PER0MODRST_SDMMCOCP |
- AGX_RSTMGR_PER0MODRST_DMAOCP);
-
- mmio_clrbits_32(AGX_RSTMGR_PER0MODRST,
- AGX_RSTMGR_PER0MODRST_EMAC0 |
- AGX_RSTMGR_PER0MODRST_EMAC1 |
- AGX_RSTMGR_PER0MODRST_EMAC2 |
- AGX_RSTMGR_PER0MODRST_USB0 |
- AGX_RSTMGR_PER0MODRST_USB1 |
- AGX_RSTMGR_PER0MODRST_NAND |
- AGX_RSTMGR_PER0MODRST_SDMMC |
- AGX_RSTMGR_PER0MODRST_DMA |
- AGX_RSTMGR_PER0MODRST_SPIM0 |
- AGX_RSTMGR_PER0MODRST_SPIM1 |
- AGX_RSTMGR_PER0MODRST_SPIS0 |
- AGX_RSTMGR_PER0MODRST_SPIS1 |
- AGX_RSTMGR_PER0MODRST_EMACPTP |
- AGX_RSTMGR_PER0MODRST_DMAIF0 |
- AGX_RSTMGR_PER0MODRST_DMAIF1 |
- AGX_RSTMGR_PER0MODRST_DMAIF2 |
- AGX_RSTMGR_PER0MODRST_DMAIF3 |
- AGX_RSTMGR_PER0MODRST_DMAIF4 |
- AGX_RSTMGR_PER0MODRST_DMAIF5 |
- AGX_RSTMGR_PER0MODRST_DMAIF6 |
- AGX_RSTMGR_PER0MODRST_DMAIF7);
-
- mmio_clrbits_32(AGX_RSTMGR_BRGMODRST,
- AGX_RSTMGR_BRGMODRST_MPFE);
-}
-
-void config_hps_hs_before_warm_reset(void)
-{
- uint32_t or_mask = 0;
-
- or_mask |= AGX_RSTMGR_HDSKEN_SDRSELFREFEN;
- or_mask |= AGX_RSTMGR_HDSKEN_FPGAHSEN;
- or_mask |= AGX_RSTMGR_HDSKEN_ETRSTALLEN;
- or_mask |= AGX_RSTMGR_HDSKEN_L2FLUSHEN;
- or_mask |= AGX_RSTMGR_HDSKEN_L3NOC_DBG;
- or_mask |= AGX_RSTMGR_HDSKEN_DEBUG_L3NOC;
-
- mmio_setbits_32(AGX_RSTMGR_HDSKEN, or_mask);
-}
-
-static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match)
-{
- int time_out = 1000;
-
- while (time_out--) {
- if ((mmio_read_32(addr) & mask) == match) {
- return 0;
- }
- }
- return -ETIMEDOUT;
-}
-
-int socfpga_bridges_enable(void)
-{
- uint32_t status, poll_addr;
-
- status = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS);
-
- if (!status) {
- /* Clear idle request */
- mmio_setbits_32(AGX_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_CLR), ~0);
-
- /* De-assert all bridges */
- mmio_clrbits_32(AGX_RSTMGR_BRGMODRST, ~0);
-
- /* Wait until idle ack becomes 0 */
- poll_addr = AGX_SYSMGR_CORE(SYSMGR_NOC_IDLEACK);
-
- return poll_idle_status(poll_addr, IDLE_DATA_MASK, 0);
- }
- return status;
-}
-
-int socfpga_bridges_disable(void)
-{
- uint32_t poll_addr;
-
- /* Set idle request */
- mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_SET), ~0);
-
- /* Enable NOC timeout */
- mmio_setbits_32(SYSMGR_NOC_TIMEOUT, 1);
-
- /* Wait until each idle ack bit toggle to 1 */
- poll_addr = AGX_SYSMGR_CORE(SYSMGR_NOC_IDLEACK);
- if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK))
- return -ETIMEDOUT;
-
- /* Wait until each idle status bit toggle to 1 */
- poll_addr = AGX_SYSMGR_CORE(SYSMGR_NOC_IDLESTATUS);
- if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK))
- return -ETIMEDOUT;
-
- /* Assert all bridges */
- mmio_setbits_32(AGX_RSTMGR_BRGMODRST,
- ~(AGX_RSTMGR_BRGMODRST_MPFE | AGX_RSTMGR_BRGMODRST_FPGA2SOC));
-
- /* Disable NOC timeout */
- mmio_clrbits_32(AGX_SYSMGR_CORE(SYSMGR_NOC_TIMEOUT), 1);
-
- return 0;
-}