| commit | e26c59d2c968eb0122bf1c333d5ceba534d5fe45 | [log] [tgz] |
|---|---|---|
| author | johpow01 <john.powell@arm.com> | Tue Oct 06 17:55:25 2020 -0500 |
| committer | John_Powell <john.powell@arm.com> | Tue Jan 12 18:06:37 2021 +0000 |
| tree | 9d5c4b8666dbabf4581bd4d378e4b44cb77ad197 | |
| parent | 6e886a475734310f5079945be442490d146e0c04 [diff] |
Workaround for Cortex A78 erratum 1941498 Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1 register, there is a small performance cost (<0.5%) for setting this bit. SDEN can be found here: https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9