commit 3e833f8363ad6d40f35aee92b9ecea1988e44edf
author Joanna Farley <joanna.farley@arm.com> Wed Mar 15 13:14:26 2023 +0100
committer TrustedFirmware Code Review <review@review.trustedfirmware.org> Wed Mar 15 13:14:26 2023 +0100
tree 5dc778bd8aac9ac0fbe83e715fd5097f2f73b8ea
parent a4c69581aec798af796d6783b51d9a62648c8db9
parent 95bbfbc6e0789cba871e2518dba76ff9bf712331

Merge "fix(versal_net): fix irq for IPI0" into integration

plat/xilinx/versal_net/include/platform_def.h

diff --git a/plat/xilinx/versal_net/include/platform_def.h b/plat/xilinx/versal_net/include/platform_def.h
index 696771f..9aa1441 100644
--- a/plat/xilinx/versal_net/include/platform_def.h
+++ b/plat/xilinx/versal_net/include/platform_def.h
@@ -103,12 +103,15 @@
  * terminology. On a GICv2 system or mode, the lists will be merged and treated
  * as Group 0 interrupts.
  */
-#define PLAT_VERSAL_IPI_IRQ	62
+#define PLAT_VERSAL_NET_IPI_IRQ	89
+#define PLAT_VERSAL_IPI_IRQ	PLAT_VERSAL_NET_IPI_IRQ
 
 #define PLAT_VERSAL_NET_G1S_IRQ_PROPS(grp) \
 	INTR_PROP_DESC(VERSAL_NET_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
 			GIC_INTR_CFG_LEVEL)
 
-#define PLAT_VERSAL_NET_G0_IRQ_PROPS(grp)
+#define PLAT_VERSAL_NET_G0_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE), \
 
 #endif /* PLATFORM_DEF_H */