diff --git a/include/drivers/arm/gic600ae_fmu.h b/include/drivers/arm/gic600ae_fmu.h
index f7dcbb8..904a5f9 100644
--- a/include/drivers/arm/gic600ae_fmu.h
+++ b/include/drivers/arm/gic600ae_fmu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -86,10 +86,10 @@
 
 /* Safety Mechamism limit */
 #define FMU_SMID_GICD_MAX	U(33)
+#define FMU_SMID_PPI_MAX	U(12)
+#define FMU_SMID_ITS_MAX	U(14)
 #define FMU_SMID_SPICOL_MAX	U(5)
 #define FMU_SMID_WAKERQ_MAX	U(2)
-#define FMU_SMID_ITS_MAX	U(14)
-#define FMU_SMID_PPI_MAX	U(12)
 
 /* MBIST Safety Mechanism ID */
 #define GICD_MBIST_REQ_ERROR	U(23)
@@ -142,6 +142,7 @@
 void gic_fmu_write_smen(uintptr_t base, uint32_t val);
 void gic_fmu_write_sminjerr(uintptr_t base, uint32_t val);
 void gic_fmu_write_pingmask(uintptr_t base, uint64_t val);
+void gic_fmu_disable_all_sm_blkid(uintptr_t base, unsigned int blkid);
 
 void gic600_fmu_init(uint64_t base, uint64_t blk_present_mask, bool errctlr_ce_en, bool errctlr_ue_en);
 void gic600_fmu_enable_ping(uint64_t base, uint64_t blk_present_mask,