drivers: st: update drivers code
Reword some traces.
Use uintptr_t where required.
Reduce scope of variables.
Improve io_stm32image algo.
Complete some IP registers definitions.
Add failure on supported DDR (stm32mp1_ddr_init()).
Fix cache flush on cache disable (stm32mp1_ddr_setup).
Change-Id: Ie02fa71e02b9d69abc807fd5b7df233e5be6668c
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c
index 9591e37..bbee138 100644
--- a/drivers/st/gpio/stm32_gpio.c
+++ b/drivers/st/gpio/stm32_gpio.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -29,59 +29,60 @@
void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
uint32_t pull, uint32_t alternate)
{
- volatile uint32_t bank_address;
+ uintptr_t base;
if (!check_gpio(bank, pin)) {
return;
}
if (bank == GPIO_BANK_Z) {
- bank_address = STM32_GPIOZ_BANK;
+ base = STM32_GPIOZ_BANK;
} else {
- bank_address = STM32_GPIOA_BANK +
+ base = STM32_GPIOA_BANK +
(bank * STM32_GPIO_BANK_OFFSET);
}
- mmio_clrbits_32(bank_address + GPIO_MODE_OFFSET,
+ mmio_clrbits_32(base + GPIO_MODE_OFFSET,
((uint32_t)GPIO_MODE_MASK << (pin << 1)));
- mmio_setbits_32(bank_address + GPIO_MODE_OFFSET,
+ mmio_setbits_32(base + GPIO_MODE_OFFSET,
(mode & ~GPIO_OPEN_DRAIN) << (pin << 1));
if ((mode & GPIO_OPEN_DRAIN) != 0U) {
- mmio_setbits_32(bank_address + GPIO_TYPE_OFFSET,
- BIT(pin));
+ mmio_setbits_32(base + GPIO_TYPE_OFFSET, BIT(pin));
+ } else {
+ mmio_clrbits_32(base + GPIO_TYPE_OFFSET, BIT(pin));
}
- mmio_clrbits_32(bank_address + GPIO_SPEED_OFFSET,
+ mmio_clrbits_32(base + GPIO_SPEED_OFFSET,
((uint32_t)GPIO_SPEED_MASK << (pin << 1)));
- mmio_setbits_32(bank_address + GPIO_SPEED_OFFSET, speed << (pin << 1));
+ mmio_setbits_32(base + GPIO_SPEED_OFFSET, speed << (pin << 1));
- mmio_clrbits_32(bank_address + GPIO_PUPD_OFFSET,
+ mmio_clrbits_32(base + GPIO_PUPD_OFFSET,
((uint32_t)GPIO_PULL_MASK << (pin << 1)));
- mmio_setbits_32(bank_address + GPIO_PUPD_OFFSET, pull << (pin << 1));
+ mmio_setbits_32(base + GPIO_PUPD_OFFSET, pull << (pin << 1));
if (pin < GPIO_ALT_LOWER_LIMIT) {
- mmio_clrbits_32(bank_address + GPIO_AFRL_OFFSET,
+ mmio_clrbits_32(base + GPIO_AFRL_OFFSET,
((uint32_t)GPIO_ALTERNATE_MASK << (pin << 2)));
- mmio_setbits_32(bank_address + GPIO_AFRL_OFFSET,
+ mmio_setbits_32(base + GPIO_AFRL_OFFSET,
alternate << (pin << 2));
} else {
- mmio_clrbits_32(bank_address + GPIO_AFRH_OFFSET,
+ mmio_clrbits_32(base + GPIO_AFRH_OFFSET,
((uint32_t)GPIO_ALTERNATE_MASK <<
((pin - GPIO_ALT_LOWER_LIMIT) << 2)));
- mmio_setbits_32(bank_address + GPIO_AFRH_OFFSET,
+ mmio_setbits_32(base + GPIO_AFRH_OFFSET,
alternate << ((pin - GPIO_ALT_LOWER_LIMIT) <<
2));
}
VERBOSE("GPIO %u mode set to 0x%x\n", bank,
- mmio_read_32(bank_address + GPIO_MODE_OFFSET));
+ mmio_read_32(base + GPIO_MODE_OFFSET));
VERBOSE("GPIO %u speed set to 0x%x\n", bank,
- mmio_read_32(bank_address + GPIO_SPEED_OFFSET));
+ mmio_read_32(base + GPIO_SPEED_OFFSET));
VERBOSE("GPIO %u mode pull to 0x%x\n", bank,
- mmio_read_32(bank_address + GPIO_PUPD_OFFSET));
+ mmio_read_32(base + GPIO_PUPD_OFFSET));
VERBOSE("GPIO %u mode alternate low to 0x%x\n", bank,
- mmio_read_32(bank_address + GPIO_AFRL_OFFSET));
+ mmio_read_32(base + GPIO_AFRL_OFFSET));
VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank,
- mmio_read_32(bank_address + GPIO_AFRH_OFFSET));
+ mmio_read_32(base + GPIO_AFRH_OFFSET));
}