commit 46d1b09bd05c772a04e5c3f6c70672edb1c28a11
author Sona Mathew <sonarebecca.mathew@arm.com> Wed Mar 19 18:24:23 2025 -0500
committer Govindraj Raja <govindraj.raja@arm.com> Tue Apr 22 16:57:16 2025 -0500
tree a8edb4fed0dda5eda2ac99b0f4302a52b205f89e
parent ba6840c6e02c23369dde4ec60bc56c38677c0762

chore(cpus): rearrange the errata and cve in order in Cortex-X4

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Cortex-X4.

Change-Id: Ic304c2f68e7d0b96bbb30760696b7bceabe1ae2d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
(cherry picked from commit ede127e66c8946d2f5dafbda60558f11ba50841c)
Signed-off-by: Chris Palmer <palmer@google.com>

lib/cpus/aarch64/cortex_a65ae.S

diff --git a/lib/cpus/aarch64/cortex_a65ae.S b/lib/cpus/aarch64/cortex_a65ae.S
index f1a63b0..dfe6f95 100644
--- a/lib/cpus/aarch64/cortex_a65ae.S
+++ b/lib/cpus/aarch64/cortex_a65ae.S
@@ -10,8 +10,8 @@
 #include <common/debug.h>
 #include <cortex_a65ae.h>
 #include <cpu_macros.S>
-#include <plat_macros.S>
 #include <dsu_macros.S>
+#include <plat_macros.S>
 
 /* Hardware handled coherency */
 #if !HW_ASSISTED_COHERENCY

lib/cpus/aarch64/cortex_x4.S

diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index 53461c6..74687a9 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -35,13 +35,6 @@
 
 check_erratum_ls cortex_x4, ERRATUM(2726228), CPU_REV(0, 1)
 
-/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
-workaround_reset_start cortex_x4, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
-	sysreg_bit_set CORTEX_X4_CPUECTLR_EL1, BIT(46)
-workaround_reset_end cortex_x4, CVE(2024, 5660)
-
-check_erratum_ls cortex_x4, CVE(2024, 5660), CPU_REV(0, 2)
-
 workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
 	/* dsb before isb of power down sequence */
 	dsb	sy
@@ -100,6 +93,10 @@
 
 check_erratum_ls cortex_x4, ERRATUM(3076789), CPU_REV(0, 1)
 
+add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758
+
+check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3)
+
 workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 #if IMAGE_BL31
 	/*
@@ -112,6 +109,13 @@
 
 check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 
+/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
+workaround_reset_start cortex_x4, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
+	sysreg_bit_set CORTEX_X4_CPUECTLR_EL1, BIT(46)
+workaround_reset_end cortex_x4, CVE(2024, 5660)
+
+check_erratum_ls cortex_x4, CVE(2024, 5660), CPU_REV(0, 2)
+
 workaround_reset_start cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
 	/* ---------------------------------
 	 * Sets BIT41 of CPUACTLR6_EL1 which
@@ -123,10 +127,6 @@
 
 check_erratum_chosen cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
 
-add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758
-
-check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3)
-
 cpu_reset_func_start cortex_x4
 	/* Disable speculative loads */
 	msr	SSBS, xzr

lib/cpus/errata_common.c

diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index 0530647..df9a3d7 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c
@@ -8,9 +8,9 @@
 
 #include <arch.h>
 #include <arch_helpers.h>
-#include <cortex_a75.h>
 #include <cortex_a510.h>
 #include <cortex_a520.h>
+#include <cortex_a75.h>
 #include <cortex_a710.h>
 #include <cortex_a715.h>
 #include <cortex_a720.h>