diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index 07796c7..60b1231 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -50,22 +50,6 @@
 	 *	Numeric value expected to read from CPU's MIDR
 	 * _resetfunc:
 	 *	Reset function for the CPU.
-	 * _extra1:
-	 *	This is a placeholder for future per CPU operations.  Currently,
-	 *	some CPUs use this entry to set a test function to determine if
-	 *	the workaround for CVE-2017-5715 needs to be applied or not.
-	 * _extra2:
-	 *	This is a placeholder for future per CPU operations. Currently
-	 *	some CPUs use this entry to set a function to disable the
-	 *	workaround for CVE-2018-3639.
-	 * _extra3:
-	 *	This is a placeholder for future per CPU operations. Currently,
-	 *	some CPUs use this entry to set a test function to determine if
-	 *	the workaround for CVE-2022-23960 needs to be applied or not.
-	 * _extra4:
-	 *	This is a placeholder for future per CPU operations. Currently,
-	 *	some CPUs use this entry to set a test function to determine if
-	 *	the workaround for CVE-2024-7881 needs to be applied or not.
 	 * _e_handler:
 	 *	This is a placeholder for future per CPU exception handlers.
 	 * _power_down_ops:
@@ -78,7 +62,6 @@
 	 *	used to handle power down at subsequent levels
 	 */
 	.macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \
-		_extra1:req, _extra2:req, _extra3:req, _extra4:req, \
 		_e_handler:req, _power_down_ops:vararg
 	.section .cpu_ops, "a"
 	.align 3
@@ -87,10 +70,6 @@
 #if defined(IMAGE_AT_EL3)
 	.quad \_resetfunc
 #endif
-	.quad \_extra1
-	.quad \_extra2
-	.quad \_extra3
-	.quad \_extra4
 	.quad \_e_handler
 #ifdef IMAGE_BL31
 	/* Insert list of functions */
@@ -153,28 +132,13 @@
 
 	.macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
 		_power_down_ops:vararg
-		declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, 0, 0, 0, \
-			\_power_down_ops
+		declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, \_power_down_ops
 	.endm
 
 	.macro declare_cpu_ops_eh _name:req, _midr:req, _resetfunc:req, \
 		_e_handler:req, _power_down_ops:vararg
 		declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
-			0, 0, 0, 0, \_e_handler, \_power_down_ops
-	.endm
-
-	.macro declare_cpu_ops_wa _name:req, _midr:req, \
-		_resetfunc:req, _extra1:req, _extra2:req, \
-		_extra3:req, _power_down_ops:vararg
-		declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
-			\_extra1, \_extra2, \_extra3, 0, 0, \_power_down_ops
-	.endm
-
-	.macro declare_cpu_ops_wa_4 _name:req, _midr:req, \
-		_resetfunc:req, _extra1:req, _extra2:req, \
-		_extra3:req, _extra4:req, _power_down_ops:vararg
-		declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
-			\_extra1, \_extra2, \_extra3, \_extra4, 0, \_power_down_ops
+			\_e_handler, \_power_down_ops
 	.endm
 
 	/*
@@ -240,7 +204,7 @@
  *	Default value is 0.
  */
 .macro add_erratum_entry _cpu:req, _cve:req, _id:req, _chosen:req, _split_wa=0
-#if REPORT_ERRATA || ERRATA_ABI_SUPPORT
+#if INCLUDE_ERRATA_LIST
 	.pushsection .rodata.errata_entries
 		.align	3
 		.ifndef \_cpu\()_errata_list_start
diff --git a/include/lib/cpus/cpu_ops.h b/include/lib/cpus/cpu_ops.h
index 0b08919..5ba78cf 100644
--- a/include/lib/cpus/cpu_ops.h
+++ b/include/lib/cpus/cpu_ops.h
@@ -22,14 +22,6 @@
 /* The number of CPU operations allowed */
 #define CPU_MAX_PWR_DWN_OPS		2
 
-#if __aarch64__
-#define CPU_NO_EXTRA1_FUNC		0
-#define CPU_NO_EXTRA2_FUNC		0
-#define CPU_NO_EXTRA3_FUNC		0
-#define CPU_NO_EXTRA4_FUNC		0
-#endif /* __aarch64__ */
-
-
 /*
  * Define the sizes of the fields in the cpu_ops structure. Word size is set per
  * Aarch so keep these definitions the same and each can include whatever it
@@ -41,10 +33,6 @@
 #else
 #define CPU_RESET_FUNC_SIZE	0
 #endif /* IMAGE_AT_EL3 */
-#define CPU_EXTRA1_FUNC_SIZE	CPU_WORD_SIZE
-#define CPU_EXTRA2_FUNC_SIZE	CPU_WORD_SIZE
-#define CPU_EXTRA3_FUNC_SIZE	CPU_WORD_SIZE
-#define CPU_EXTRA4_FUNC_SIZE	CPU_WORD_SIZE
 #define CPU_E_HANDLER_FUNC_SIZE CPU_WORD_SIZE
 /* The power down core and cluster is needed only in BL31 and BL32 */
 #if defined(IMAGE_BL31) || defined(IMAGE_BL32)
@@ -86,11 +74,7 @@
 #define CPU_MIDR		0
 #define CPU_RESET_FUNC		CPU_MIDR + CPU_MIDR_SIZE
 #if __aarch64__
-#define CPU_EXTRA1_FUNC		CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
-#define CPU_EXTRA2_FUNC		CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE
-#define CPU_EXTRA3_FUNC		CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE
-#define CPU_EXTRA4_FUNC		CPU_EXTRA3_FUNC + CPU_EXTRA3_FUNC_SIZE
-#define CPU_E_HANDLER_FUNC	CPU_EXTRA4_FUNC + CPU_EXTRA4_FUNC_SIZE
+#define CPU_E_HANDLER_FUNC	CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
 #define CPU_PWR_DWN_OPS		CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE
 #else
 #define CPU_PWR_DWN_OPS		CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
@@ -117,10 +101,6 @@
 	void (*reset_func)(void);
 #endif /* IMAGE_AT_EL3 */
 #if __aarch64__
-	void (*extra1_func)(void);
-	void (*extra2_func)(void);
-	void (*extra3_func)(void);
-	void (*extra4_func)(void);
 	void (*e_handler_func)(long es);
 #endif /* __aarch64__ */
 #if (defined(IMAGE_BL31) || defined(IMAGE_BL32)) && CPU_MAX_PWR_DWN_OPS
diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h
index 6e77156..6be54d6 100644
--- a/include/lib/cpus/errata.h
+++ b/include/lib/cpus/errata.h
@@ -27,6 +27,18 @@
 #define ERRATA_APPLIES		1
 #define ERRATA_MISSING		2
 
+/* Errata ID for smc workarounds */
+#define ARCH_WORKAROUND_2		2
+#define ARCH_WORKAROUND_3		3
+
+#define INCLUDE_ERRATA_LIST	(		\
+	REPORT_ERRATA			|	\
+	ERRATA_ABI_SUPPORT		|	\
+	WORKAROUND_CVE_2017_5715	|	\
+	WORKAROUND_CVE_2018_3639	|	\
+	WORKAROUND_CVE_2022_23960	|	\
+	WORKAROUND_CVE_2024_7881)
+
 #ifndef __ASSEMBLER__
 #include <lib/cassert.h>
 
@@ -72,6 +84,7 @@
 int check_wa_cve_2024_7881(void);
 bool errata_ich_vmcr_el2_applies(void);
 struct erratum_entry *find_erratum_entry(uint32_t errata_id);
+int check_erratum_applies(uint32_t cve, int errata_id);
 
 #else
 
@@ -84,8 +97,6 @@
  * unlikely event that this does happen, prepending the CVE id with a 0 should
  * resolve the conflict
  */
-#define ERRATUM(id)		0, id
-#define CVE(year, id)		year, id
 #define NO_ISB			1
 #define NO_ASSERT		0
 #define NO_APPLY_AT_RESET	0
@@ -98,6 +109,9 @@
 
 #endif /* __ASSEMBLER__ */
 
+#define ERRATUM(id)		0, id
+#define CVE(year, id)		year, id
+
 /* Macro to get CPU revision code for checking errata version compatibility. */
 #define CPU_REV(r, p)		((r << 4) | p)
 
diff --git a/include/lib/cpus/wa_cve_2017_5715.h b/include/lib/cpus/wa_cve_2017_5715.h
deleted file mode 100644
index 2ad56e1..0000000
--- a/include/lib/cpus/wa_cve_2017_5715.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef WA_CVE_2017_5715_H
-#define WA_CVE_2017_5715_H
-
-int check_wa_cve_2017_5715(void);
-
-#endif /* WA_CVE_2017_5715_H */
diff --git a/include/lib/cpus/wa_cve_2018_3639.h b/include/lib/cpus/wa_cve_2018_3639.h
deleted file mode 100644
index 5a7c9bf..0000000
--- a/include/lib/cpus/wa_cve_2018_3639.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef WA_CVE_2018_3639_H
-#define WA_CVE_2018_3639_H
-
-void *wa_cve_2018_3639_get_disable_ptr(void);
-
-#endif /* WA_CVE_2018_3639_H */
diff --git a/include/lib/cpus/wa_cve_2022_23960.h b/include/lib/cpus/wa_cve_2022_23960.h
deleted file mode 100644
index 50c0f76..0000000
--- a/include/lib/cpus/wa_cve_2022_23960.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef WA_CVE_2022_23960_H
-#define WA_CVE_2022_23960_H
-
-int check_smccc_arch_wa3_applies(void);
-
-#endif /* WA_CVE_2022_23960_H */
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index adacc5c..553f6f9 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -65,15 +65,20 @@
 	ret
 endfunc cortex_a57_disable_ext_debug
 
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */
+add_erratum_entry cortex_a57, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
+check_erratum_chosen cortex_a57, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
 /*
  * Disable the over-read from the LDNP/STNP instruction. The SDEN doesn't
- * provide and erratum number, so assign it an obvious 1
+ * provide and erratum number, so assign it an obvious 99999
  */
-workaround_reset_start cortex_a57, ERRATUM(1), A57_DISABLE_NON_TEMPORAL_HINT
+workaround_reset_start cortex_a57, ERRATUM(99999), A57_DISABLE_NON_TEMPORAL_HINT
 	sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
-workaround_reset_end cortex_a57, ERRATUM(1)
+workaround_reset_end cortex_a57, ERRATUM(99999)
 
-check_erratum_ls cortex_a57, ERRATUM(1), CPU_REV(1, 2)
+check_erratum_ls cortex_a57, ERRATUM(99999), CPU_REV(1, 2)
 
 workaround_reset_start cortex_a57, ERRATUM(806969), ERRATA_A57_806969
 	sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
@@ -187,11 +192,6 @@
 	sysreg_bit_set CORTEX_A57_ECTLR_EL1, CORTEX_A57_ECTLR_SMP_BIT
 cpu_reset_func_end cortex_a57
 
-func check_smccc_arch_workaround_3
-	mov	x0, #ERRATA_APPLIES
-	ret
-endfunc check_smccc_arch_workaround_3
-
 	/* ----------------------------------------------------
 	 * The CPU Ops core power down function for Cortex-A57.
 	 * ----------------------------------------------------
@@ -307,10 +307,7 @@
 	ret
 endfunc cortex_a57_cpu_reg_dump
 
-declare_cpu_ops_wa cortex_a57, CORTEX_A57_MIDR, \
+declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \
 	cortex_a57_reset_func, \
-	check_erratum_cortex_a57_5715, \
-	CPU_NO_EXTRA2_FUNC, \
-	check_smccc_arch_workaround_3, \
 	cortex_a57_core_pwr_dwn, \
 	cortex_a57_cluster_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S
index fee28ee..23b27ab 100644
--- a/lib/cpus/aarch64/cortex_a72.S
+++ b/lib/cpus/aarch64/cortex_a72.S
@@ -76,14 +76,17 @@
 	ret
 endfunc cortex_a72_disable_ext_debug
 
-func check_smccc_arch_workaround_3
+check_erratum_custom_start cortex_a72, ERRATUM(ARCH_WORKAROUND_3)
 	cpu_check_csv2	x0, 1f
 	mov	x0, #ERRATA_APPLIES
 	ret
 1:
 	mov	x0, #ERRATA_NOT_APPLIES
 	ret
-endfunc check_smccc_arch_workaround_3
+check_erratum_custom_end cortex_a72, ERRATUM(ARCH_WORKAROUND_3)
+
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */
+add_erratum_entry cortex_a72, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
 
 workaround_reset_start cortex_a72, ERRATUM(859971), ERRATA_A72_859971
 	sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH
@@ -294,10 +297,7 @@
 	ret
 endfunc cortex_a72_cpu_reg_dump
 
-declare_cpu_ops_wa cortex_a72, CORTEX_A72_MIDR, \
+declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \
 	cortex_a72_reset_func, \
-	check_erratum_cortex_a72_5715, \
-	CPU_NO_EXTRA2_FUNC, \
-	check_smccc_arch_workaround_3, \
 	cortex_a72_core_pwr_dwn, \
 	cortex_a72_cluster_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a73.S b/lib/cpus/aarch64/cortex_a73.S
index d1fc6d4..9cc6fdb 100644
--- a/lib/cpus/aarch64/cortex_a73.S
+++ b/lib/cpus/aarch64/cortex_a73.S
@@ -33,10 +33,10 @@
 	ret
 endfunc cortex_a73_disable_smp
 
-func check_smccc_arch_workaround_3
-	mov	x0, #ERRATA_APPLIES
-	ret
-endfunc check_smccc_arch_workaround_3
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */
+add_erratum_entry cortex_a73, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
+check_erratum_chosen cortex_a73, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
 
 workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427
 	sysreg_bit_set CORTEX_A73_DIAGNOSTIC_REGISTER, BIT(12)
@@ -200,10 +200,7 @@
 	ret
 endfunc cortex_a73_cpu_reg_dump
 
-declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \
+declare_cpu_ops cortex_a73, CORTEX_A73_MIDR, \
 	cortex_a73_reset_func, \
-	check_erratum_cortex_a73_5715, \
-	CPU_NO_EXTRA2_FUNC, \
-	check_smccc_arch_workaround_3, \
 	cortex_a73_core_pwr_dwn, \
 	cortex_a73_cluster_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S
index 13599ca..ef9c067 100644
--- a/lib/cpus/aarch64/cortex_a75.S
+++ b/lib/cpus/aarch64/cortex_a75.S
@@ -20,6 +20,11 @@
 
 cpu_reset_prologue cortex_a75
 
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */
+add_erratum_entry cortex_a75, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
+check_erratum_chosen cortex_a75, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
 workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081
 	sysreg_bit_set sctlr_el3, SCTLR_IESB_BIT
 workaround_reset_end cortex_a75, ERRATUM(764081)
@@ -131,11 +136,6 @@
 #endif
 cpu_reset_func_end cortex_a75
 
-func check_smccc_arch_workaround_3
-	mov	x0, #ERRATA_APPLIES
-	ret
-endfunc check_smccc_arch_workaround_3
-
 	/* ---------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ---------------------------------------------
@@ -170,9 +170,6 @@
 	ret
 endfunc cortex_a75_cpu_reg_dump
 
-declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \
+declare_cpu_ops cortex_a75, CORTEX_A75_MIDR, \
 	cortex_a75_reset_func, \
-	check_erratum_cortex_a75_5715, \
-	CPU_NO_EXTRA2_FUNC, \
-	check_smccc_arch_workaround_3, \
 	cortex_a75_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 36bb0ca..24c62a7 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -301,6 +301,11 @@
 endfunc apply_cve_2018_3639_sync_wa
 #endif /* DYNAMIC_WORKAROUND_CVE_2018_3639 */
 
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_2*/
+add_erratum_entry cortex_a76, ERRATUM(ARCH_WORKAROUND_2), WORKAROUND_CVE_2018_3639
+
+check_erratum_chosen cortex_a76, ERRATUM(ARCH_WORKAROUND_2), WORKAROUND_CVE_2018_3639
+
 workaround_reset_start cortex_a76, ERRATUM(798953), ERRATA_DSU_798953
 	errata_dsu_798953_wa_impl
 workaround_reset_end cortex_a76, ERRATUM(798953)
@@ -531,9 +536,6 @@
 	ret
 endfunc cortex_a76_cpu_reg_dump
 
-declare_cpu_ops_wa cortex_a76, CORTEX_A76_MIDR, \
+declare_cpu_ops cortex_a76, CORTEX_A76_MIDR, \
 	cortex_a76_reset_func, \
-	CPU_NO_EXTRA1_FUNC, \
-	cortex_a76_disable_wa_cve_2018_3639, \
-	CPU_NO_EXTRA3_FUNC, \
 	cortex_a76_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index 81ff9ed..f486a83 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -166,10 +166,6 @@
 	ret
 endfunc cortex_x3_cpu_reg_dump
 
-declare_cpu_ops_wa_4 cortex_x3, CORTEX_X3_MIDR, \
+declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \
 	cortex_x3_reset_func, \
-	CPU_NO_EXTRA1_FUNC, \
-	CPU_NO_EXTRA2_FUNC, \
-	CPU_NO_EXTRA3_FUNC, \
-	check_erratum_cortex_x3_7881, \
 	cortex_x3_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index 74687a9..df117bf 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -168,10 +168,6 @@
 	ret
 endfunc cortex_x4_cpu_reg_dump
 
-declare_cpu_ops_wa_4 cortex_x4, CORTEX_X4_MIDR, \
+declare_cpu_ops cortex_x4, CORTEX_X4_MIDR, \
 	cortex_x4_reset_func, \
-	CPU_NO_EXTRA1_FUNC, \
-	CPU_NO_EXTRA2_FUNC, \
-	CPU_NO_EXTRA3_FUNC, \
-	check_erratum_cortex_x4_7881, \
 	cortex_x4_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x925.S b/lib/cpus/aarch64/cortex_x925.S
index 7dec375..6c852dd 100644
--- a/lib/cpus/aarch64/cortex_x925.S
+++ b/lib/cpus/aarch64/cortex_x925.S
@@ -98,10 +98,6 @@
 	ret
 endfunc cortex_x925_cpu_reg_dump
 
-declare_cpu_ops_wa_4 cortex_x925, CORTEX_X925_MIDR, \
+declare_cpu_ops cortex_x925, CORTEX_X925_MIDR, \
 	cortex_x925_reset_func, \
-	CPU_NO_EXTRA1_FUNC, \
-	CPU_NO_EXTRA2_FUNC, \
-	CPU_NO_EXTRA3_FUNC, \
-	check_erratum_cortex_x925_7881, \
 	cortex_x925_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S
index e608422..105da5c 100644
--- a/lib/cpus/aarch64/cpu_helpers.S
+++ b/lib/cpus/aarch64/cpu_helpers.S
@@ -188,143 +188,3 @@
 	get_rev_var x0, x1
 	ret
 endfunc cpu_get_rev_var
-
-/*
- * int check_wa_cve_2017_5715(void);
- *
- * This function returns:
- *  - ERRATA_APPLIES when firmware mitigation is required.
- *  - ERRATA_NOT_APPLIES when firmware mitigation is _not_ required.
- *  - ERRATA_MISSING when firmware mitigation would be required but
- *    is not compiled in.
- *
- * NOTE: Must be called only after cpu_ops have been initialized
- *       in per-CPU data.
- */
-	.globl	check_wa_cve_2017_5715
-func check_wa_cve_2017_5715
-	mrs	x0, tpidr_el3
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif
-	ldr	x0, [x0, #CPU_DATA_CPU_OPS_PTR]
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif
-	ldr	x0, [x0, #CPU_EXTRA1_FUNC]
-	/*
-	 * If the reserved function pointer is NULL, this CPU
-	 * is unaffected by CVE-2017-5715 so bail out.
-	 */
-	cmp	x0, #CPU_NO_EXTRA1_FUNC
-	beq	1f
-	br	x0
-1:
-	mov	x0, #ERRATA_NOT_APPLIES
-	ret
-endfunc check_wa_cve_2017_5715
-
-/*
- * int check_wa_cve_2024_7881(void);
- *
- * This function returns:
- *  - ERRATA_APPLIES when firmware mitigation is required.
- *  - ERRATA_NOT_APPLIES when firmware mitigation is _not_ required.
- *  - ERRATA_MISSING when firmware mitigation would be required but
- *    is not compiled in.
- *
- * NOTE: Must be called only after cpu_ops have been initialized
- *       in per-CPU data.
- */
-.globl	check_wa_cve_2024_7881
-func check_wa_cve_2024_7881
-	mrs	x0, tpidr_el3
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif
-	ldr	x0, [x0, #CPU_DATA_CPU_OPS_PTR]
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif
-	ldr	x0, [x0, #CPU_EXTRA4_FUNC]
-	/*
-	 * If the reserved function pointer is NULL, this CPU
-	 * is unaffected by CVE-2024-7881 so bail out.
-	 */
-	cmp	x0, #CPU_NO_EXTRA4_FUNC
-	beq	1f
-	br	x0
-1:
-	mov	x0, #ERRATA_NOT_APPLIES
-	ret
-endfunc check_wa_cve_2024_7881
-
-/*
- * void *wa_cve_2018_3639_get_disable_ptr(void);
- *
- * Returns a function pointer which is used to disable mitigation
- * for CVE-2018-3639.
- * The function pointer is only returned on cores that employ
- * dynamic mitigation.  If the core uses static mitigation or is
- * unaffected by CVE-2018-3639 this function returns NULL.
- *
- * NOTE: Must be called only after cpu_ops have been initialized
- *       in per-CPU data.
- */
-	.globl	wa_cve_2018_3639_get_disable_ptr
-func wa_cve_2018_3639_get_disable_ptr
-	mrs	x0, tpidr_el3
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif
-	ldr	x0, [x0, #CPU_DATA_CPU_OPS_PTR]
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif
-	ldr	x0, [x0, #CPU_EXTRA2_FUNC]
-	ret
-endfunc wa_cve_2018_3639_get_disable_ptr
-
-/*
- * int check_smccc_arch_wa3_applies(void);
- *
- * This function checks whether SMCCC_ARCH_WORKAROUND_3 is enabled to mitigate
- * CVE-2022-23960 for this CPU. It returns:
- *  - ERRATA_APPLIES when SMCCC_ARCH_WORKAROUND_3 can be invoked to mitigate
- *    the CVE.
- *  - ERRATA_NOT_APPLIES when SMCCC_ARCH_WORKAROUND_3 should not be invoked to
- *    mitigate the CVE.
- *
- * NOTE: Must be called only after cpu_ops have been initialized
- *       in per-CPU data.
- */
-	.globl	check_smccc_arch_wa3_applies
-func check_smccc_arch_wa3_applies
-	mrs	x0, tpidr_el3
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif
-	ldr	x0, [x0, #CPU_DATA_CPU_OPS_PTR]
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif
-	ldr	x0, [x0, #CPU_EXTRA3_FUNC]
-	/*
-	 * If the reserved function pointer is NULL, this CPU
-	 * is unaffected by CVE-2022-23960 so bail out.
-	 */
-	cmp	x0, #CPU_NO_EXTRA3_FUNC
-	beq	1f
-	br	x0
-1:
-	mov	x0, #ERRATA_NOT_APPLIES
-	ret
-endfunc check_smccc_arch_wa3_applies
diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S
index 64158e7..22cd3ba 100644
--- a/lib/cpus/aarch64/denver.S
+++ b/lib/cpus/aarch64/denver.S
@@ -319,11 +319,8 @@
 
 /* macro to declare cpu_ops for Denver SKUs */
 .macro	denver_cpu_ops_wa midr
-	declare_cpu_ops_wa denver, \midr, \
+	declare_cpu_ops denver, \midr, \
 		denver_reset_func, \
-		check_erratum_denver_5715, \
-		CPU_NO_EXTRA2_FUNC, \
-		CPU_NO_EXTRA3_FUNC, \
 		denver_core_pwr_dwn, \
 		denver_cluster_pwr_dwn
 .endm
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S
index ce84942..9526b80 100644
--- a/lib/cpus/aarch64/neoverse_v2.S
+++ b/lib/cpus/aarch64/neoverse_v2.S
@@ -148,10 +148,6 @@
 	ret
 endfunc neoverse_v2_cpu_reg_dump
 
-declare_cpu_ops_wa_4 neoverse_v2, NEOVERSE_V2_MIDR, \
+declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \
 	neoverse_v2_reset_func, \
-	CPU_NO_EXTRA1_FUNC, \
-	CPU_NO_EXTRA2_FUNC, \
-	CPU_NO_EXTRA3_FUNC, \
-	check_erratum_neoverse_v2_7881, \
 	neoverse_v2_core_pwr_dwn
diff --git a/lib/cpus/aarch64/neoverse_v3.S b/lib/cpus/aarch64/neoverse_v3.S
index 2ead062..ca108e7 100644
--- a/lib/cpus/aarch64/neoverse_v3.S
+++ b/lib/cpus/aarch64/neoverse_v3.S
@@ -124,10 +124,6 @@
 	neoverse_v3_reset_func, \
 	neoverse_v3_core_pwr_dwn
 
-declare_cpu_ops_wa_4 neoverse_v3, NEOVERSE_V3_MIDR, \
+declare_cpu_ops neoverse_v3, NEOVERSE_V3_MIDR, \
 	neoverse_v3_reset_func, \
-	CPU_NO_EXTRA1_FUNC, \
-	CPU_NO_EXTRA2_FUNC, \
-	CPU_NO_EXTRA3_FUNC, \
-	check_erratum_neoverse_v3_7881, \
 	neoverse_v3_core_pwr_dwn
diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index 7da2075..97801dd 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c
@@ -178,3 +178,21 @@
 
 	return false;
 }
+
+int check_erratum_applies(uint32_t cve, int errata_id)
+{
+	struct erratum_entry *entry;
+	long rev_var;
+
+	rev_var = cpu_get_rev_var();
+
+	entry = find_erratum_entry(errata_id);
+
+	if (entry == NULL) {
+		return ERRATA_NOT_APPLIES;
+	}
+
+	assert(entry->cve == cve);
+
+	return entry->check_func(rev_var);
+}
diff --git a/plat/qti/common/src/aarch64/qti_kryo4_gold.S b/plat/qti/common/src/aarch64/qti_kryo4_gold.S
index 49b7cf0..61eb755 100644
--- a/plat/qti/common/src/aarch64/qti_kryo4_gold.S
+++ b/plat/qti/common/src/aarch64/qti_kryo4_gold.S
@@ -59,9 +59,7 @@
 	ret
 endfunc qti_kryo4_gold_cpu_reg_dump
 
-declare_cpu_ops_wa	qti_kryo4_gold, QTI_KRYO4_GOLD_MIDR,	\
+declare_cpu_ops	qti_kryo4_gold, QTI_KRYO4_GOLD_MIDR,	\
 		qti_kryo4_gold_reset_func,		\
-		CPU_NO_EXTRA1_FUNC,		\
-		cortex_a76_disable_wa_cve_2018_3639,	\
 		cortex_a76_core_pwr_dwn,	\
 		qti_kryo4_gold_cluster_pwr_dwn
diff --git a/services/arm_arch_svc/arm_arch_svc_setup.c b/services/arm_arch_svc/arm_arch_svc_setup.c
index 740f7e2..dbb118c 100644
--- a/services/arm_arch_svc/arm_arch_svc_setup.c
+++ b/services/arm_arch_svc/arm_arch_svc_setup.c
@@ -7,9 +7,6 @@
 #include <common/debug.h>
 #include <common/runtime_svc.h>
 #include <lib/cpus/errata.h>
-#include <lib/cpus/wa_cve_2017_5715.h>
-#include <lib/cpus/wa_cve_2018_3639.h>
-#include <lib/cpus/wa_cve_2022_23960.h>
 #include <lib/smccc.h>
 #include <services/arm_arch_svc.h>
 #include <smccc_helpers.h>
@@ -32,8 +29,11 @@
 	/* Workaround checks are currently only implemented for aarch64 */
 #if WORKAROUND_CVE_2017_5715
 	case SMCCC_ARCH_WORKAROUND_1:
-		if (check_wa_cve_2017_5715() == ERRATA_NOT_APPLIES)
+		if (check_erratum_applies(CVE(2017, 5715))
+			== ERRATA_NOT_APPLIES) {
 			return 1;
+		}
+
 		return 0; /* ERRATA_APPLIES || ERRATA_MISSING */
 #endif
 
@@ -63,8 +63,10 @@
 		 * or permanently mitigated, report the latter as not
 		 * needing dynamic mitigation.
 		 */
-		if (wa_cve_2018_3639_get_disable_ptr() == NULL)
+		if (check_erratum_applies(ERRATUM(ARCH_WORKAROUND_2))
+			== ERRATA_NOT_APPLIES)
 			return 1;
+
 		/*
 		 * If we get here, this CPU requires dynamic mitigation
 		 * so report it as such.
@@ -84,16 +86,19 @@
 		 * CVE-2017-5715 since this SMC can be used instead of
 		 * SMCCC_ARCH_WORKAROUND_1.
 		 */
-		if ((check_smccc_arch_wa3_applies() == ERRATA_NOT_APPLIES) &&
-		    (check_wa_cve_2017_5715() == ERRATA_NOT_APPLIES)) {
+		if ((check_erratum_applies(ERRATUM(ARCH_WORKAROUND_3))
+			== ERRATA_NOT_APPLIES) &&
+		    (check_erratum_applies(CVE(2017, 5715))
+			== ERRATA_NOT_APPLIES)) {
 			return 1;
 		}
+
 		return 0; /* ERRATA_APPLIES || ERRATA_MISSING */
 #endif
 
 #if WORKAROUND_CVE_2024_7881
 	case SMCCC_ARCH_WORKAROUND_4:
-		if (check_wa_cve_2024_7881() != ERRATA_APPLIES) {
+		if (check_erratum_applies(CVE(2024, 7881)) != ERRATA_APPLIES) {
 			return SMC_ARCH_CALL_NOT_SUPPORTED;
 		}
 		return 0;