diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 5291684..5e21673 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -61,6 +61,14 @@
 #define MPIDR_AFFLVL1		1
 #define MPIDR_AFFLVL2		2
 #define MPIDR_AFFLVL3		3
+#define MPIDR_AFFLVL0_VAL(mpidr) \
+		((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
+#define MPIDR_AFFLVL1_VAL(mpidr) \
+		((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
+#define MPIDR_AFFLVL2_VAL(mpidr) \
+		((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
+#define MPIDR_AFFLVL3_VAL(mpidr) \
+		((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
 /*
  * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
  * add one while using this macro to define array sizes.
diff --git a/plat/fvp/aarch64/fvp_common.c b/plat/fvp/aarch64/fvp_common.c
index ddaacba..a8afb4e 100644
--- a/plat/fvp/aarch64/fvp_common.c
+++ b/plat/fvp/aarch64/fvp_common.c
@@ -32,7 +32,7 @@
 #include <arch_helpers.h>
 #include <arm_gic.h>
 #include <bl_common.h>
-#include <cci400.h>
+#include <cci.h>
 #include <debug.h>
 #include <mmio.h>
 #include <platform.h>
@@ -295,6 +295,12 @@
 	return counter_base_frequency;
 }
 
+/* Map of CCI masters with the slave interfaces they are connected */
+static const int cci_map[] = {
+	CCI400_CLUSTER0_SL_IFACE_IX,
+	CCI400_CLUSTER1_SL_IFACE_IX
+};
+
 void fvp_cci_init(void)
 {
 	/*
@@ -302,19 +308,20 @@
 	 */
 	if (plat_config.flags & CONFIG_HAS_CCI)
 		cci_init(CCI400_BASE,
-			CCI400_SL_IFACE3_CLUSTER_IX,
-			CCI400_SL_IFACE4_CLUSTER_IX);
+			cci_map,
+			ARRAY_SIZE(cci_map));
 }
 
 void fvp_cci_enable(void)
 {
-	/*
-	 * Enable CCI-400 coherency for this cluster. No need
-	 * for locks as no other cpu is active at the
-	 * moment
-	 */
 	if (plat_config.flags & CONFIG_HAS_CCI)
-		cci_enable_cluster_coherency(read_mpidr());
+		cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
+}
+
+void fvp_cci_disable(void)
+{
+	if (plat_config.flags & CONFIG_HAS_CCI)
+		cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
 }
 
 void fvp_gic_init(void)
diff --git a/plat/fvp/fvp_def.h b/plat/fvp/fvp_def.h
index e3442fc..a2f2da8 100644
--- a/plat/fvp/fvp_def.h
+++ b/plat/fvp/fvp_def.h
@@ -236,8 +236,8 @@
  * CCI-400 related constants
  ******************************************************************************/
 #define CCI400_BASE			0x2c090000
-#define CCI400_SL_IFACE3_CLUSTER_IX	0
-#define CCI400_SL_IFACE4_CLUSTER_IX	1
+#define CCI400_CLUSTER0_SL_IFACE_IX	3
+#define CCI400_CLUSTER1_SL_IFACE_IX	4
 
 /*******************************************************************************
  * GIC-400 & interrupt handling related constants
diff --git a/plat/fvp/fvp_pm.c b/plat/fvp/fvp_pm.c
index c15d845..3737ecf 100644
--- a/plat/fvp/fvp_pm.c
+++ b/plat/fvp/fvp_pm.c
@@ -32,7 +32,7 @@
 #include <arm_gic.h>
 #include <assert.h>
 #include <bakery_lock.h>
-#include <cci400.h>
+#include <cci.h>
 #include <debug.h>
 #include <mmio.h>
 #include <platform.h>
@@ -82,8 +82,7 @@
 	uint64_t mpidr = read_mpidr_el1();
 
 	/* Disable coherency if this cluster is to be turned off */
-	if (get_plat_config()->flags & CONFIG_HAS_CCI)
-		cci_disable_cluster_coherency(mpidr);
+	fvp_cci_disable();
 
 	/* Program the power controller to turn the cluster off */
 	fvp_pwrc_write_pcoffr(mpidr);
diff --git a/plat/fvp/fvp_private.h b/plat/fvp/fvp_private.h
index 3949754..4f60a16 100644
--- a/plat/fvp/fvp_private.h
+++ b/plat/fvp/fvp_private.h
@@ -138,6 +138,7 @@
 
 void fvp_cci_init(void);
 void fvp_cci_enable(void);
+void fvp_cci_disable(void);
 
 void fvp_gic_init(void);
 
diff --git a/plat/fvp/include/plat_macros.S b/plat/fvp/include/plat_macros.S
index f050261..9e5ef4d 100644
--- a/plat/fvp/include/plat_macros.S
+++ b/plat/fvp/include/plat_macros.S
@@ -27,7 +27,7 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
-#include <cci400.h>
+#include <cci.h>
 #include <gic_v2.h>
 #include <plat_config.h>
 #include "../fvp_def.h"
diff --git a/plat/fvp/platform.mk b/plat/fvp/platform.mk
index bcee328..7cf571e 100644
--- a/plat/fvp/platform.mk
+++ b/plat/fvp/platform.mk
@@ -57,7 +57,7 @@
 				plat/common/aarch64/plat_common.c		\
 				plat/fvp/fvp_io_storage.c
 
-BL1_SOURCES		+=	drivers/arm/cci400/cci400.c			\
+BL1_SOURCES		+=	drivers/arm/cci/cci.c				\
 				lib/cpus/aarch64/aem_generic.S			\
 				lib/cpus/aarch64/cortex_a53.S			\
 				lib/cpus/aarch64/cortex_a57.S			\
@@ -72,7 +72,7 @@
 				plat/fvp/fvp_security.c				\
 				plat/fvp/aarch64/fvp_common.c
 
-BL31_SOURCES		+=	drivers/arm/cci400/cci400.c			\
+BL31_SOURCES		+=	drivers/arm/cci/cci.c				\
 				drivers/arm/gic/arm_gic.c			\
 				drivers/arm/gic/gic_v2.c			\
 				drivers/arm/gic/gic_v3.c			\
diff --git a/plat/juno/aarch64/juno_common.c b/plat/juno/aarch64/juno_common.c
index 371323e..6b6e185 100644
--- a/plat/juno/aarch64/juno_common.c
+++ b/plat/juno/aarch64/juno_common.c
@@ -32,6 +32,7 @@
 #include <arm_gic.h>
 #include <assert.h>
 #include <bl_common.h>
+#include <cci.h>
 #include <debug.h>
 #include <mmio.h>
 #include <platform.h>
@@ -136,6 +137,18 @@
 	IRQ_SEC_SGI_7
 };
 
+static const int cci_map[] = {
+	CCI400_CLUSTER0_SL_IFACE_IX,
+	CCI400_CLUSTER1_SL_IFACE_IX
+};
+
+void plat_cci_init(void)
+{
+	cci_init(CCI400_BASE,
+		cci_map,
+		ARRAY_SIZE(cci_map));
+}
+
 /*******************************************************************************
  * Macro generating the code for the function setting up the pagetables as per
  * the platform memory map & initialize the mmu, for the given exception level
diff --git a/plat/juno/bl1_plat_setup.c b/plat/juno/bl1_plat_setup.c
index 23e8592..fd331bf 100644
--- a/plat/juno/bl1_plat_setup.c
+++ b/plat/juno/bl1_plat_setup.c
@@ -31,7 +31,7 @@
 #include <arch_helpers.h>
 #include <assert.h>
 #include <bl_common.h>
-#include <cci400.h>
+#include <cci.h>
 #include <console.h>
 #include <debug.h>
 #include <mmio.h>
@@ -82,10 +82,8 @@
 	 * Enable CCI-400 for this cluster. No need for locks as no other cpu is
 	 * active at the moment
 	 */
-	cci_init(CCI400_BASE,
-		 CCI400_SL_IFACE3_CLUSTER_IX,
-		 CCI400_SL_IFACE4_CLUSTER_IX);
-	cci_enable_cluster_coherency(read_mpidr());
+	plat_cci_init();
+	cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
 
 	/* Allow BL1 to see the whole Trusted RAM */
 	bl1_tzram_layout.total_base = TZRAM_BASE;
diff --git a/plat/juno/bl31_plat_setup.c b/plat/juno/bl31_plat_setup.c
index 1d33768..194d620 100644
--- a/plat/juno/bl31_plat_setup.c
+++ b/plat/juno/bl31_plat_setup.c
@@ -33,7 +33,7 @@
 #include <assert.h>
 #include <bl31.h>
 #include <bl_common.h>
-#include <cci400.h>
+#include <cci.h>
 #include <console.h>
 #include <mmio.h>
 #include <platform.h>
@@ -123,9 +123,7 @@
 	 * a warm boot. BL1 should have already enabled CCI coherency for this
 	 * cluster during cold boot.
 	 */
-	cci_init(CCI400_BASE,
-		 CCI400_SL_IFACE3_CLUSTER_IX,
-		 CCI400_SL_IFACE4_CLUSTER_IX);
+	plat_cci_init();
 
 	/*
 	 * Check params passed from BL2 should not be NULL,
diff --git a/plat/juno/include/plat_macros.S b/plat/juno/include/plat_macros.S
index a9d2466..ac1077b 100644
--- a/plat/juno/include/plat_macros.S
+++ b/plat/juno/include/plat_macros.S
@@ -28,7 +28,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <cci400.h>
+#include <cci.h>
 #include <gic_v2.h>
 #include "platform_def.h"
 #include "../juno_def.h"
diff --git a/plat/juno/juno_def.h b/plat/juno/juno_def.h
index 62bdda3..ab39f3c 100644
--- a/plat/juno/juno_def.h
+++ b/plat/juno/juno_def.h
@@ -261,8 +261,8 @@
  * CCI-400 related constants
  ******************************************************************************/
 #define CCI400_BASE			0x2c090000
-#define CCI400_SL_IFACE3_CLUSTER_IX	1
-#define CCI400_SL_IFACE4_CLUSTER_IX	0
+#define CCI400_CLUSTER0_SL_IFACE_IX	4
+#define CCI400_CLUSTER1_SL_IFACE_IX	3
 
 /*******************************************************************************
  * SCP <=> AP boot configuration
diff --git a/plat/juno/juno_private.h b/plat/juno/juno_private.h
index 9a5944c..afb1bfc 100644
--- a/plat/juno/juno_private.h
+++ b/plat/juno/juno_private.h
@@ -154,6 +154,7 @@
 unsigned long platform_get_stack(unsigned long mpidr);
 uint64_t plat_get_syscnt_freq(void);
 void plat_gic_init(void);
+void plat_cci_init(void);
 
 /* Declarations for plat_topology.c */
 int plat_setup_topology(void);
diff --git a/plat/juno/plat_pm.c b/plat/juno/plat_pm.c
index 47338cf..953e5f7 100644
--- a/plat/juno/plat_pm.c
+++ b/plat/juno/plat_pm.c
@@ -31,8 +31,8 @@
 #include <assert.h>
 #include <arch_helpers.h>
 #include <arm_gic.h>
+#include <cci.h>
 #include <debug.h>
-#include <cci400.h>
 #include <errno.h>
 #include <platform.h>
 #include <platform_def.h>
@@ -159,8 +159,7 @@
 	 * if this cluster was off.
 	 */
 	if (afflvl != MPIDR_AFFLVL0)
-		cci_enable_cluster_coherency(mpidr);
-
+		cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
 
 	/* Enable the gic cpu interface */
 	arm_gic_cpuif_setup();
@@ -187,7 +186,7 @@
 
 	/* Cluster is to be turned off, so disable coherency */
 	if (afflvl > MPIDR_AFFLVL0) {
-		cci_disable_cluster_coherency(read_mpidr_el1());
+		cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
 		cluster_state = scpi_power_off;
 	}
 
diff --git a/plat/juno/platform.mk b/plat/juno/platform.mk
index 8beaecf..9e44b23 100644
--- a/plat/juno/platform.mk
+++ b/plat/juno/platform.mk
@@ -56,7 +56,7 @@
 				plat/common/plat_gic.c			\
 				plat/juno/plat_io_storage.c
 
-BL1_SOURCES		+=	drivers/arm/cci400/cci400.c		\
+BL1_SOURCES		+=	drivers/arm/cci/cci.c			\
 				lib/cpus/aarch64/cortex_a53.S		\
 				lib/cpus/aarch64/cortex_a57.S		\
 				plat/common/aarch64/platform_up_stack.S	\
@@ -75,7 +75,7 @@
 				plat/juno/scp_bootloader.c		\
 				plat/juno/scpi.c
 
-BL31_SOURCES		+=	drivers/arm/cci400/cci400.c		\
+BL31_SOURCES		+=	drivers/arm/cci/cci.c			\
 				drivers/arm/gic/arm_gic.c		\
 				drivers/arm/gic/gic_v2.c		\
 				drivers/arm/gic/gic_v3.c		\