intel: agilex: Fix reliance on hard coded clock information
Extract clock information for UART, MMC & Watchdog from the clock manager
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I42d3d4ceeaf45788d457472f6ddcd3fe099f0133
diff --git a/plat/intel/soc/agilex/include/agilex_private.h b/plat/intel/soc/agilex/include/agilex_private.h
index 5ccbc8c..fc0e9fd 100644
--- a/plat/intel/soc/agilex/include/agilex_private.h
+++ b/plat/intel/soc/agilex/include/agilex_private.h
@@ -11,14 +11,13 @@
#define AGX_MMC_REG_BASE 0xff808000
#define EMMC_DESC_SIZE (1<<20)
-#define EMMC_INIT_PARAMS(base) \
+#define EMMC_INIT_PARAMS(base, clk) \
{ .bus_width = MMC_BUS_WIDTH_4, \
- .clk_rate = 50000000, \
+ .clk_rate = (clk), \
.desc_base = (base), \
.desc_size = EMMC_DESC_SIZE, \
.flags = 0, \
- .reg_base = AGX_MMC_REG_BASE, \
- \
+ .reg_base = AGX_MMC_REG_BASE \
}
typedef enum {
@@ -26,7 +25,7 @@
BOOT_SOURCE_SDMMC,
BOOT_SOURCE_NAND,
BOOT_SOURCE_RSVD,
- BOOT_SOURCE_QSPI,
+ BOOT_SOURCE_QSPI
} boot_source_type;
void enable_nonsecure_access(void);