)]}' { "commit": "5016ee44a740127f7865dc26ed0efbbff1481c7e", "tree": "11cd560aec9f9b628e5b98d823f1cfafe6d39c17", "parents": [ "30df8904d0f6973bbce1ecb51f14c1e4725ddf0b" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Thu Mar 24 11:56:30 2022 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue Jul 19 11:45:10 2022 +0100" }, "message": "fix(morello): dts: fix SMMU IRQ ordering\n\nThe official SMMUv3 DT bindings require a certain order of the\ninterrupts, Linux\u0027 \"make dtbs_check\" reports:\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n.../morello-soc.dt.yaml: iommu@4f400000: interrupt-names: \u0027oneOf\u0027 conditional failed, one must be fixed:\n [\u0027eventq\u0027, \u0027priq\u0027, \u0027cmdq-sync\u0027, \u0027gerror\u0027] is too long\n \u0027combined\u0027 was expected\n \u0027gerror\u0027 was expected\n \u0027priq\u0027 was expected\n \u0027cmdq-sync\u0027 was expected\n From schema: Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\nSwap the order of the interrupt-names and their corresponding interrupts\nvalues to improve bindings compliance.\n\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nChange-Id: I2110b8509593a4f1aadff11bd518ec4a0f3f5d3c\n", "tree_diff": [ { "type": "modify", "old_id": "2f9865bd99bea8e18e7b15703006783a4d8d3d1a", "old_mode": 33188, "old_path": "fdts/morello-soc.dts", "new_id": "64742f167ba777fa1892d20b9ad0fd981281abd9", "new_mode": 33188, "new_path": "fdts/morello-soc.dts" } ] }