Add support for asynchronous FIQ handling in TSP
This patch adds support in the TSP to handle FIQ interrupts that are
generated when execution is in the TSP. S-EL1 interrupt are handled
normally and execution resumes at the instruction where the exception
was originally taken. S-EL3 interrupts i.e. any interrupt not
recognized by the TSP are handed to the TSPD. Execution resumes
normally once such an interrupt has been handled at EL3.
Change-Id: Ia3ada9a4fb15670afcc12538a6456f21efe58a8f
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S
index bb0880f..54276f2 100644
--- a/bl32/tsp/aarch64/tsp_entrypoint.S
+++ b/bl32/tsp/aarch64/tsp_entrypoint.S
@@ -87,7 +87,7 @@
* Set the exception vector to something sane.
* ---------------------------------------------
*/
- adr x0, early_exceptions
+ adr x0, tsp_exceptions
msr vbar_el1, x0
/* ---------------------------------------------
@@ -184,7 +184,7 @@
* Set the exception vector to something sane.
* ---------------------------------------------
*/
- adr x0, early_exceptions
+ adr x0, tsp_exceptions
msr vbar_el1, x0
/* ---------------------------------------------