commit 5cf6fafe223da89c60e2323c242ea188b17e98c3
author Christine Gharzuzi <chrisg@marvell.com> Wed Jul 25 16:06:10 2018 +0300
committer Konstantin Porotchkin <kostap@marvell.com> Tue Dec 04 14:09:44 2018 +0200
tree 271d81f0652202b06d09b07e3dba37d1b50dc1ab
parent c35442690cbf4316151c039fb0ccdac2a39ad40a

fix: a3900: pm: fix number of CPU power switches.

- Number of open power switches for CPUs should be three
  and now two.

- This patch updates the value of open power switches from
  0xfd (two power-switches) to 0xfc (three power-switches).

Change-Id: I2783ab7f04bbbb6da78eeedcabe4636f9a774512
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

plat/marvell/a8k/common/plat_pm.c

diff --git a/plat/marvell/a8k/common/plat_pm.c b/plat/marvell/a8k/common/plat_pm.c
index 1b68d07..2854416 100644
--- a/plat/marvell/a8k/common/plat_pm.c
+++ b/plat/marvell/a8k/common/plat_pm.c
@@ -79,7 +79,7 @@
 	#define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET		1
 	#define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET	0
 #else
-#define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET		0
+	#define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET		0
 	#define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET	31
 #endif
 
@@ -106,7 +106,7 @@
 #define AP807_PWRC_LDO_CR0_OFFSET		16
 #define AP807_PWRC_LDO_CR0_MASK			\
 			(0xff << AP807_PWRC_LDO_CR0_OFFSET)
-#define AP807_PWRC_LDO_CR0_VAL			0xfd
+#define AP807_PWRC_LDO_CR0_VAL			0xfc
 
 /*
  * Power down CPU: