tree d4af3aeee5040bb2f39f5c087d5316723247b653
parent 02a9d70c4deaa2102386611ac6b305838003148d
author Jit Loon Lim <jit.loon.lim@intel.com> 1671717156 +0800
committer Sieu Mun Tang <sieu.mun.tang@intel.com> 1681435171 +0800

fix(intel): fix Agilex and N5X clock manager to main PLL C0

Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ to
PLAT_HZ_CONVERT_TO_MHZ.
2. Updated get_cpu_clk to point to get_mpu_clk and added comment.
3. Added get_mpu_clk to get clock from main PLL C0 and Peri PLL C0.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I43a9d83caa832b61eba93a830e2a671fd4dffa19