diff --git a/plat/intel/soc/common/aarch64/plat_helpers.S b/plat/intel/soc/common/aarch64/plat_helpers.S
index 213fd3c..6bf2d82 100644
--- a/plat/intel/soc/common/aarch64/plat_helpers.S
+++ b/plat/intel/soc/common/aarch64/plat_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
index 99d48d2..bebb289 100644
--- a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
+++ b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +10,8 @@
 #include <lib/mmio.h>
 
 #include "ncore_ccu.h"
+#include "socfpga_plat_def.h"
+#include "socfpga_system_manager.h"
 
 uint32_t poll_active_bit(uint32_t dir);
 
diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h
index 4e50156..78deebc 100644
--- a/plat/intel/soc/common/include/platform_def.h
+++ b/plat/intel/soc/common/include/platform_def.h
@@ -12,12 +12,15 @@
 #include <common/interrupt_props.h>
 #include <common/tbbr/tbbr_img_def.h>
 #include <plat/common/common_def.h>
+#include "socfpga_plat_def.h"
 
 /* Platform Type */
 #define PLAT_SOCFPGA_STRATIX10			1
 #define PLAT_SOCFPGA_AGILEX			2
 #define PLAT_SOCFPGA_N5X			3
-#define PLAT_SOCFPGA_EMULATOR			0
+#define PLAT_SOCFPGA_AGILEX5			4
+#define SIMICS_RUN				1
+#define MAX_IO_MTD_DEVICES			U(1)
 
 /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */
 #define PLAT_CPU_RELEASE_ADDR			0xffd12210
@@ -32,8 +35,20 @@
 #define L2_RESET_DONE_STATUS			0x1228E5E7
 
 /* Define next boot image name and offset */
+/* Get non-secure image entrypoint for BL33. Zephyr and Linux */
+#if	PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+
+#ifndef PRELOADED_BL33_BASE
+#define PLAT_NS_IMAGE_OFFSET			0x80200000
+#else
+#define PLAT_NS_IMAGE_OFFSET			PRELOADED_BL33_BASE
+#endif
+#define PLAT_HANDOFF_OFFSET 0x0003F000
+
+#else
 #define PLAT_NS_IMAGE_OFFSET			0x10000000
 #define PLAT_HANDOFF_OFFSET			0xFFE3F000
+#endif
 
 /*******************************************************************************
  * Platform binary types for linking
@@ -49,7 +64,6 @@
 /*******************************************************************************
  * Generic platform constants
  ******************************************************************************/
-#define PLAT_PRIMARY_CPU			0
 #define PLAT_SECONDARY_ENTRY_BASE		0x01f78bf0
 
 /* Size of cacheable stacks */
@@ -64,49 +78,27 @@
 #define PLATFORM_CLUSTER_COUNT			U(1)
 #define PLATFORM_CLUSTER0_CORE_COUNT		U(4)
 #define PLATFORM_CLUSTER1_CORE_COUNT		U(0)
-#define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER1_CORE_COUNT + \
-					PLATFORM_CLUSTER0_CORE_COUNT)
+#define PLATFORM_CORE_COUNT			(PLATFORM_CLUSTER1_CORE_COUNT + \
+						PLATFORM_CLUSTER0_CORE_COUNT)
 #define PLATFORM_MAX_CPUS_PER_CLUSTER		U(4)
 
 /* Interrupt related constant */
 
 #define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER		29
 
-#define INTEL_SOCFPGA_IRQ_SEC_SGI_0			8
-#define INTEL_SOCFPGA_IRQ_SEC_SGI_1			9
-#define INTEL_SOCFPGA_IRQ_SEC_SGI_2			10
-#define INTEL_SOCFPGA_IRQ_SEC_SGI_3			11
-#define INTEL_SOCFPGA_IRQ_SEC_SGI_4			12
-#define INTEL_SOCFPGA_IRQ_SEC_SGI_5			13
-#define INTEL_SOCFPGA_IRQ_SEC_SGI_6			14
-#define INTEL_SOCFPGA_IRQ_SEC_SGI_7			15
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_0		8
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_1		9
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_2		10
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_3		11
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_4		12
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_5		13
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_6		14
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_7		15
 
-#define TSP_IRQ_SEC_PHY_TIMER		INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER
-#define TSP_SEC_MEM_BASE		BL32_BASE
-#define TSP_SEC_MEM_SIZE		(BL32_LIMIT - BL32_BASE + 1)
-/*******************************************************************************
- * Platform memory map related constants
- ******************************************************************************/
-#define DRAM_BASE				(0x0)
-#define DRAM_SIZE				(0x80000000)
+#define TSP_IRQ_SEC_PHY_TIMER			INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER
+#define TSP_SEC_MEM_BASE			BL32_BASE
+#define TSP_SEC_MEM_SIZE			(BL32_LIMIT - BL32_BASE + 1)
 
-#define OCRAM_BASE				(0xFFE00000)
-#define OCRAM_SIZE				(0x00040000)
-
-#define MEM64_BASE				(0x0100000000)
-#define MEM64_SIZE				(0x1F00000000)
-
-#define DEVICE1_BASE				(0x80000000)
-#define DEVICE1_SIZE				(0x60000000)
-
-#define DEVICE2_BASE				(0xF7000000)
-#define DEVICE2_SIZE				(0x08E00000)
-
-#define DEVICE3_BASE				(0xFFFC0000)
-#define DEVICE3_SIZE				(0x00008000)
-
-#define DEVICE4_BASE				(0x2000000000)
-#define DEVICE4_SIZE				(0x0100000000)
 
 /*******************************************************************************
  * BL31 specific defines.
@@ -117,33 +109,28 @@
  * little space for growth.
  */
 
+#define FIRMWARE_WELCOME_STR			"Booting Trusted Firmware\n"
 
-#define FIRMWARE_WELCOME_STR	"Booting Trusted Firmware\n"
+#define BL1_RO_BASE				(0xffe00000)
+#define BL1_RO_LIMIT				(0xffe0f000)
+#define BL1_RW_BASE				(0xffe10000)
+#define BL1_RW_LIMIT				(0xffe1ffff)
+#define BL1_RW_SIZE				(0x14000)
 
-#define BL1_RO_BASE		(0xffe00000)
-#define BL1_RO_LIMIT		(0xffe0f000)
-#define BL1_RW_BASE		(0xffe10000)
-#define BL1_RW_LIMIT		(0xffe1ffff)
-#define BL1_RW_SIZE		(0x14000)
+#define BL_DATA_LIMIT				PLAT_HANDOFF_OFFSET
 
-#define BL2_BASE		(0xffe00000)
-#define BL2_LIMIT		(0xffe1b000)
+#define PLAT_CPUID_RELEASE			(BL_DATA_LIMIT - 16)
+#define PLAT_SEC_ENTRY				(BL_DATA_LIMIT - 8)
 
-#define BL31_BASE		(0x1000)
-#define BL31_LIMIT		(0x81000)
+#define CMP_ENTRY				0xFFE3EFF8
 
-#define BL_DATA_LIMIT		PLAT_HANDOFF_OFFSET
-
-#define PLAT_CPUID_RELEASE	(BL_DATA_LIMIT - 16)
-#define PLAT_SEC_ENTRY		(BL_DATA_LIMIT - 8)
-
-#define PLAT_SEC_WARM_ENTRY	0
+#define PLAT_SEC_WARM_ENTRY			0
 
 /*******************************************************************************
  * Platform specific page table and MMU setup constants
  ******************************************************************************/
-#define MAX_XLAT_TABLES			8
-#define MAX_MMAP_REGIONS		16
+#define MAX_XLAT_TABLES				8
+#define MAX_MMAP_REGIONS			16
 
 /*******************************************************************************
  * Declarations and constants to access the mailboxes safely. Each mailbox is
@@ -155,46 +142,34 @@
  * a valid mailbox address.
  ******************************************************************************/
 #define CACHE_WRITEBACK_SHIFT			6
-#define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
-
-#define PLAT_GIC_BASE			(0xFFFC0000)
-#define PLAT_GICC_BASE			(PLAT_GIC_BASE + 0x2000)
-#define PLAT_GICD_BASE			(PLAT_GIC_BASE + 0x1000)
-#define PLAT_GICR_BASE			0
+#define CACHE_WRITEBACK_GRANULE			(1 << CACHE_WRITEBACK_SHIFT)
 
 /*******************************************************************************
  * UART related constants
  ******************************************************************************/
-#define PLAT_UART0_BASE		(0xFFC02000)
-#define PLAT_UART1_BASE		(0xFFC02100)
+#define CRASH_CONSOLE_BASE			PLAT_UART0_BASE
+#define PLAT_INTEL_UART_BASE			PLAT_UART0_BASE
 
-#define CRASH_CONSOLE_BASE	PLAT_UART0_BASE
-#define PLAT_INTEL_UART_BASE	PLAT_UART0_BASE
-
-#if PLAT_SOCFPGA_EMULATOR
-#define PLAT_BAUDRATE		(4800)
-#define PLAT_UART_CLOCK		(76800)
-#else
-#define PLAT_BAUDRATE		(115200)
-#define PLAT_UART_CLOCK		(100000000)
-#endif
+#define PLAT_BAUDRATE				(115200)
+#define PLAT_UART_CLOCK				(100000000)
 
 /*******************************************************************************
  * PHY related constants
  ******************************************************************************/
 
-#define EMAC0_PHY_MODE			PHY_INTERFACE_MODE_RGMII
-#define EMAC1_PHY_MODE			PHY_INTERFACE_MODE_RGMII
-#define EMAC2_PHY_MODE			PHY_INTERFACE_MODE_RGMII
+#define EMAC0_PHY_MODE				PHY_INTERFACE_MODE_RGMII
+#define EMAC1_PHY_MODE				PHY_INTERFACE_MODE_RGMII
+#define EMAC2_PHY_MODE				PHY_INTERFACE_MODE_RGMII
+
+/*******************************************************************************
+ * GIC related constants
+ ******************************************************************************/
+#define PLAT_INTEL_SOCFPGA_GICD_BASE		PLAT_GICD_BASE
+#define PLAT_INTEL_SOCFPGA_GICC_BASE		PLAT_GICC_BASE
 
 /*******************************************************************************
  * System counter frequency related constants
  ******************************************************************************/
-#define PLAT_SYS_COUNTER_FREQ_IN_TICKS	(400000000)
-#define PLAT_HZ_CONVERT_TO_MHZ	(1000000)
-
-#define PLAT_INTEL_SOCFPGA_GICD_BASE	PLAT_GICD_BASE
-#define PLAT_INTEL_SOCFPGA_GICC_BASE	PLAT_GICC_BASE
 
 /*
  * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
@@ -223,9 +198,9 @@
 
 #define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp)
 
-#define MAX_IO_HANDLES			4
-#define MAX_IO_DEVICES			4
-#define MAX_IO_BLOCK_DEVICES		2
+#define MAX_IO_HANDLES				4
+#define MAX_IO_DEVICES				4
+#define MAX_IO_BLOCK_DEVICES			2
 
 #ifndef __ASSEMBLER__
 struct socfpga_bl31_params {
@@ -239,4 +214,3 @@
 #endif
 
 #endif /* PLATFORM_DEF_H */
-
diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h
index 69ee6d3..8d9ba70 100644
--- a/plat/intel/soc/common/include/socfpga_system_manager.h
+++ b/plat/intel/soc/common/include/socfpga_system_manager.h
@@ -13,26 +13,6 @@
 
 #define SOCFPGA_SYSMGR_SDMMC				0x28
 
-#define SOCFPGA_SYSMGR_FPGAINTF_EN_2			0x6c
-
-#define SOCFPGA_SYSMGR_EMAC_0				0x44
-#define SOCFPGA_SYSMGR_EMAC_1				0x48
-#define SOCFPGA_SYSMGR_EMAC_2				0x4c
-#define SOCFPGA_SYSMGR_FPGAINTF_EN_3			0x70
-
-#define SOCFPGA_SYSMGR_NOC_TIMEOUT			0xc0
-#define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET			0xc4
-#define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR			0xc8
-#define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL			0xcc
-#define SOCFPGA_SYSMGR_NOC_IDLEACK			0xd0
-#define SOCFPGA_SYSMGR_NOC_IDLESTATUS			0xd4
-
-#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0		0x200
-#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1		0x204
-#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2		0x208
-#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_8		0x220
-#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_9		0x224
-
 /* Field Masking */
 
 #define SYSMGR_SDMMC_DRVSEL(x)			(((x) & 0x7) << 0)
diff --git a/plat/intel/soc/common/sip/socfpga_sip_ecc.c b/plat/intel/soc/common/sip/socfpga_sip_ecc.c
index c4e06a6..c444d48 100644
--- a/plat/intel/soc/common/sip/socfpga_sip_ecc.c
+++ b/plat/intel/soc/common/sip/socfpga_sip_ecc.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved.
  */
 
 #include <assert.h>
@@ -11,10 +11,12 @@
 
 #include "socfpga_fcs.h"
 #include "socfpga_mailbox.h"
+#include "socfpga_plat_def.h"
 #include "socfpga_reset_manager.h"
 #include "socfpga_sip_svc.h"
 #include "socfpga_system_manager.h"
 
+
 uint32_t intel_ecc_dbe_notification(uint64_t dbe_value)
 {
 	dbe_value &= WARM_RESET_WFI_FLAG;
diff --git a/plat/intel/soc/common/soc/socfpga_emac.c b/plat/intel/soc/common/soc/socfpga_emac.c
index cacfd53..02ff89e 100644
--- a/plat/intel/soc/common/soc/socfpga_emac.c
+++ b/plat/intel/soc/common/soc/socfpga_emac.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2020-2023, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,7 @@
 #include <platform_def.h>
 
 #include "socfpga_emac.h"
+#include "socfpga_plat_def.h"
 #include "socfpga_reset_manager.h"
 #include "socfpga_system_manager.h"
 
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index 7010d81..5c99872 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2020-2023, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,8 +7,10 @@
 #include <lib/mmio.h>
 #include <common/debug.h>
 #include <drivers/delay_timer.h>
+#include <platform_def.h>
 
 #include "socfpga_mailbox.h"
+#include "socfpga_plat_def.h"
 #include "socfpga_sip_svc.h"
 #include "socfpga_system_manager.h"
 
diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c
index 77d9a73..a546638 100644
--- a/plat/intel/soc/common/soc/socfpga_reset_manager.c
+++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,9 +8,11 @@
 #include <common/debug.h>
 #include <drivers/delay_timer.h>
 #include <lib/mmio.h>
+#include <platform_def.h>
 
 #include "socfpga_f2sdram_manager.h"
 #include "socfpga_mailbox.h"
+#include "socfpga_plat_def.h"
 #include "socfpga_reset_manager.h"
 #include "socfpga_system_manager.h"
 
diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c
index bdece93..3b96dfc 100644
--- a/plat/intel/soc/common/socfpga_psci.c
+++ b/plat/intel/soc/common/socfpga_psci.c
@@ -1,12 +1,16 @@
 /*
- * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <arch_helpers.h>
 #include <common/debug.h>
+#ifndef SOCFPGA_GIC_V3
 #include <drivers/arm/gicv2.h>
+#else
+#include <drivers/arm/gicv3.h>
+#endif
 #include <lib/mmio.h>
 #include <lib/psci/psci.h>
 #include <plat/common/platform.h>
@@ -14,8 +18,8 @@
 #include "socfpga_mailbox.h"
 #include "socfpga_plat_def.h"
 #include "socfpga_reset_manager.h"
-#include "socfpga_system_manager.h"
 #include "socfpga_sip_svc.h"
+#include "socfpga_system_manager.h"
 
 
 /*******************************************************************************
@@ -146,11 +150,11 @@
 
 	memcpy(addr_buf, &intel_rsu_update_address,
 			sizeof(intel_rsu_update_address));
-
-	if (intel_rsu_update_address)
+	if (intel_rsu_update_address) {
 		mailbox_rsu_update(addr_buf);
-	else
+	} else {
 		mailbox_reset_cold();
+	}
 
 	while (1)
 		wfi();
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 79f743f..90cb90a 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,9 +12,10 @@
 
 #include "socfpga_fcs.h"
 #include "socfpga_mailbox.h"
+#include "socfpga_plat_def.h"
 #include "socfpga_reset_manager.h"
 #include "socfpga_sip_svc.h"
-
+#include "socfpga_system_manager.h"
 
 /* Total buffer the driver can hold */
 #define FPGA_CONFIG_BUFFER_SIZE 4
diff --git a/plat/intel/soc/common/socfpga_storage.c b/plat/intel/soc/common/socfpga_storage.c
index a2f2c18..79e15d7 100644
--- a/plat/intel/soc/common/socfpga_storage.c
+++ b/plat/intel/soc/common/socfpga_storage.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */