Merge changes I8ca411d5,Ib5f5dd81,I0488e22c into integration
* changes:
plat: imx: imx8qm: apply clk/pinmux configuration for DEBUG_CONSOLE
plat: imx: imx8qm: provide debug uart num as build param
plat: imx: imx8_iomux: fix shift-overflow errors
diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c
index 9da2f9a..e947838 100644
--- a/bl32/tsp/tsp_main.c
+++ b/bl32/tsp/tsp_main.c
@@ -371,12 +371,16 @@
tsp_stats[linear_id].smc_count++;
tsp_stats[linear_id].eret_count++;
+#if LOG_LEVEL >= LOG_LEVEL_INFO
+ spin_lock(&console_lock);
INFO("TSP: cpu 0x%lx received %s smc 0x%llx\n", read_mpidr(),
((func >> 31) & 1) == 1 ? "fast" : "yielding",
func);
INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", read_mpidr(),
tsp_stats[linear_id].smc_count,
tsp_stats[linear_id].eret_count);
+ spin_unlock(&console_lock);
+#endif
/* Render secure services and obtain results here */
results[0] = arg1;
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 2bf5eb7..9e55e60 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -217,6 +217,17 @@
:G: `grandpaul`_
:F: docs/plat/rpi3.rst
:F: plat/rpi/rpi3/
+:F: plat/rpi/common/
+:F: drivers/rpi3/
+:F: include/drivers/rpi3/
+
+Raspberry Pi 4 platform port
+----------------------------
+:M: Andre Przywara <andre.przywara@arm.com>
+:G: `Andre-ARM`_
+:F: docs/plat/rpi4.rst
+:F: plat/rpi/rpi4/
+:F: plat/rpi/common/
:F: drivers/rpi3/
:F: include/drivers/rpi3/
diff --git a/docs/components/fconf.rst b/docs/components/fconf.rst
index 4ea1f5b..38566008 100644
--- a/docs/components/fconf.rst
+++ b/docs/components/fconf.rst
@@ -99,3 +99,30 @@
registered with ``FCONF_REGISTER_POPULATOR()`` as described above.
.. uml:: ../resources/diagrams/plantuml/fconf_bl2_populate.puml
+
+Namespace guidance
+~~~~~~~~~~~~~~~~~~
+
+As mentioned above, properties are logically grouped around namespaces and
+sub-namespaces. The following concepts should be considered when adding new
+properties/namespaces.
+The framework differentiates two types of properties:
+ - Properties used inside common code.
+ - Properties used inside platform specific code.
+
+The first category applies to properties being part of the firmware and shared
+across multiple platforms. They should be globally accessible and defined
+inside the ``lib/fconf`` directory. The namespace must be chosen to reflect the
+feature/data abstracted.
+Example:
+ - |TBBR| related properties: tbbr.cot.bl2_id
+ - Dynamic configuration information: dyn_cfg.dtb_info.hw_config_id
+
+The second category should represent the majority of the properties defined
+within the framework: Platform specific properties. They must be accessed only
+within the platform API and are defined only inside the platform scope. The
+namespace must contain the platform name under which the properties defined
+belong.
+Example:
+ - Arm io framework: arm.io_policies.bl31_id
+
diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst
index d634d2e7..d6572f5 100644
--- a/docs/getting_started/porting-guide.rst
+++ b/docs/getting_started/porting-guide.rst
@@ -1116,6 +1116,35 @@
the log output. The implementation should be robust to future changes that
increase the number of log levels.
+Function : plat_get_soc_version()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ Argument : void
+ Return : int32_t
+
+This function returns soc version which mainly consist of below fields
+
+::
+
+ soc_version[30:24] = JEP-106 continuation code for the SiP
+ soc_version[23:16] = JEP-106 identification code with parity bit for the SiP
+
+Function : plat_get_soc_revision()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ Argument : void
+ Return : int32_t
+
+This function returns soc revision in below format
+
+::
+
+ soc_revision[0:30] = SOC revision of specific SOC
+
Modifications specific to a Boot Loader stage
---------------------------------------------
diff --git a/docs/plat/hikey.rst b/docs/plat/hikey.rst
index 372d388..6c488b8 100644
--- a/docs/plat/hikey.rst
+++ b/docs/plat/hikey.rst
@@ -26,9 +26,6 @@
- l-loader:
`link <https://github.com/96boards-hikey/l-loader/tree/testing/hikey960_v1.2>`__
-- uefi-tools:
- `link <https://git.linaro.org/uefi/uefi-tools.git>`__
-
- atf-fastboot:
`link <https://github.com/96boards-hikey/atf-fastboot/tree/master>`__
@@ -45,7 +42,6 @@
git clone https://github.com/96boards-hikey/edk2 -b testing/hikey960_v2.5
git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
- git clone https://git.linaro.org/uefi/uefi-tools
git clone https://github.com/96boards-hikey/atf-fastboot
- Create the symbol link to OpenPlatformPkg in edk2.
@@ -57,13 +53,12 @@
- Prepare AARCH64 && AARCH32 toolchain. Prepare python.
-- If your hikey hardware is built by CircuitCo, update *uefi-tools/platform.config* first. *(optional)*
- **Uncomment the below sentence. Otherwise, UEFI can't output messages on serial
+- If your hikey hardware is built by CircuitCo, update *OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKey.dsc* first. *(optional)*
console on hikey.**
.. code:: shell
- BUILDFLAGS=-DSERIAL_BASE=0xF8015000
+ DEFINE SERIAL_BASE=0xF8015000
If your hikey hardware is built by LeMaker, nothing to do.
@@ -71,19 +66,8 @@
.. code:: shell
- BUILD_OPTION=DEBUG
- export AARCH64_TOOLCHAIN=GCC5
- export UEFI_TOOLS_DIR=${BUILD_PATH}/uefi-tools
- export EDK2_DIR=${BUILD_PATH}/edk2
- EDK2_OUTPUT_DIR=${EDK2_DIR}/Build/HiKey/${BUILD_OPTION}_${AARCH64_TOOLCHAIN}
- # Build fastboot for Trusted Firmware-A. It's used for recovery mode.
- cd ${BUILD_PATH}/atf-fastboot
- CROSS_COMPILE=aarch64-linux-gnu- make PLAT=hikey DEBUG=1
- # Convert DEBUG/RELEASE to debug/release
- FASTBOOT_BUILD_OPTION=$(echo ${BUILD_OPTION} | tr '[A-Z]' '[a-z]')
- cd ${EDK2_DIR}
- # Build UEFI & Trusted Firmware-A
- ${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware -s ../optee_os hikey
+ cd {BUILD_PATH}/arm-trusted-firmware
+ sh ../l-loader/build_uefi.sh hikey
- Generate l-loader.bin and partition table for aosp. The eMMC capacity is either 8GB or 4GB. Just change "aosp-8g" to "linux-8g" for debian.
diff --git a/docs/plat/hikey960.rst b/docs/plat/hikey960.rst
index 3d42a77..982c2c8 100644
--- a/docs/plat/hikey960.rst
+++ b/docs/plat/hikey960.rst
@@ -26,9 +26,6 @@
- l-loader:
`link <https://github.com/96boards-hikey/l-loader/tree/testing/hikey960_v1.2>`__
-- uefi-tools:
- `link <https://git.linaro.org/uefi/uefi-tools.git>`__
-
Build Procedure
~~~~~~~~~~~~~~~
@@ -42,7 +39,6 @@
git clone https://github.com/96boards-hikey/edk2 -b testing/hikey960_v2.5
git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
- git clone https://git.linaro.org/uefi/uefi-tools
- Create the symbol link to OpenPlatformPkg in edk2.
@@ -53,13 +49,11 @@
- Prepare AARCH64 toolchain.
-- If your hikey960 hardware is v1, update *uefi-tools/platform.config* first. *(optional)*
- **Uncomment the below sentence. Otherwise, UEFI can't output messages on serial
- console on hikey960 v1.**
+- If your hikey960 hardware is v1, update *OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960.dsc* first. *(optional)*
.. code:: shell
- BUILDFLAGS=-DSERIAL_BASE=0xFDF05000
+ DEFINE SERIAL_BASE=0xFDF05000
If your hikey960 hardware is v2 or newer, nothing to do.
@@ -67,14 +61,8 @@
.. code:: shell
- BUILD_OPTION=DEBUG
- export AARCH64_TOOLCHAIN=GCC5
- export UEFI_TOOLS_DIR=${BUILD_PATH}/uefi-tools
- export EDK2_DIR=${BUILD_PATH}/edk2
- EDK2_OUTPUT_DIR=${EDK2_DIR}/Build/HiKey960/${BUILD_OPTION}_${AARCH64_TOOLCHAIN}
- cd ${EDK2_DIR}
- # Build UEFI & Trusted Firmware-A
- ${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware -s ../optee_os hikey960
+ cd {BUILD_PATH}/arm-trusted-firmware
+ sh ../l-loader/build_uefi.sh hikey960
- Generate l-loader.bin and partition table.
*Make sure that you're using the sgdisk in the l-loader directory.*
diff --git a/drivers/rpi3/gpio/rpi3_gpio.c b/drivers/rpi3/gpio/rpi3_gpio.c
index b39808f..f938f56 100644
--- a/drivers/rpi3/gpio/rpi3_gpio.c
+++ b/drivers/rpi3/gpio/rpi3_gpio.c
@@ -11,7 +11,7 @@
#include <drivers/delay_timer.h>
#include <drivers/rpi3/gpio/rpi3_gpio.h>
-static struct rpi3_gpio_params rpi3_gpio_params;
+static uintptr_t reg_base;
static int rpi3_gpio_get_direction(int gpio);
static void rpi3_gpio_set_direction(int gpio, int direction);
@@ -43,7 +43,6 @@
int rpi3_gpio_get_select(int gpio)
{
int ret;
- uintptr_t reg_base = rpi3_gpio_params.reg_base;
int regN = gpio / 10;
int shift = 3 * (gpio % 10);
uintptr_t reg_sel = reg_base + RPI3_GPIO_GPFSEL(regN);
@@ -69,7 +68,6 @@
*/
void rpi3_gpio_set_select(int gpio, int fsel)
{
- uintptr_t reg_base = rpi3_gpio_params.reg_base;
int regN = gpio / 10;
int shift = 3 * (gpio % 10);
uintptr_t reg_sel = reg_base + RPI3_GPIO_GPFSEL(regN);
@@ -106,7 +104,6 @@
static int rpi3_gpio_get_value(int gpio)
{
- uintptr_t reg_base = rpi3_gpio_params.reg_base;
int regN = gpio / 32;
int shift = gpio % 32;
uintptr_t reg_lev = reg_base + RPI3_GPIO_GPLEV(regN);
@@ -119,7 +116,6 @@
static void rpi3_gpio_set_value(int gpio, int value)
{
- uintptr_t reg_base = rpi3_gpio_params.reg_base;
int regN = gpio / 32;
int shift = gpio % 32;
uintptr_t reg_set = reg_base + RPI3_GPIO_GPSET(regN);
@@ -137,7 +133,6 @@
static void rpi3_gpio_set_pull(int gpio, int pull)
{
- uintptr_t reg_base = rpi3_gpio_params.reg_base;
int regN = gpio / 32;
int shift = gpio % 32;
uintptr_t reg_pud = reg_base + RPI3_GPIO_GPPUD;
@@ -161,9 +156,8 @@
mmio_write_32(reg_pud, 0x0);
}
-void rpi3_gpio_init(struct rpi3_gpio_params *params)
+void rpi3_gpio_init(void)
{
- assert(params != 0);
- memcpy(&rpi3_gpio_params, params, sizeof(struct rpi3_gpio_params));
+ reg_base = RPI3_GPIO_BASE;
gpio_init(&rpi3_gpio_ops);
}
diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S
index 7559de4..4fd746d 100644
--- a/include/arch/aarch32/el3_common_macros.S
+++ b/include/arch/aarch32/el3_common_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -329,6 +329,11 @@
bl inv_dcache_range
#endif
+ /*
+ * zeromem uses r12 whereas it is used to save previous BL arg3,
+ * save it in r7
+ */
+ mov r7, r12
ldr r0, =__BSS_START__
ldr r1, =__BSS_SIZE__
bl zeromem
@@ -339,6 +344,9 @@
bl zeromem
#endif
+ /* Restore r12 */
+ mov r12, r7
+
#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM)
/* -----------------------------------------------------
* Copy data from ROM to RAM.
diff --git a/include/bl32/payloads/tlk.h b/include/bl32/payloads/tlk.h
index fe6f352..5162d13 100644
--- a/include/bl32/payloads/tlk.h
+++ b/include/bl32/payloads/tlk.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,7 +27,6 @@
#define TLK_RESUME_FID TLK_TOS_YIELD_FID(0x100)
#define TLK_SYSTEM_SUSPEND TLK_TOS_YIELD_FID(0xE001)
#define TLK_SYSTEM_RESUME TLK_TOS_YIELD_FID(0xE002)
-#define TLK_SYSTEM_OFF TLK_TOS_YIELD_FID(0xE003)
#define TLK_IRQ_FIRED TLK_TOS_YIELD_FID(0xE004)
/*
@@ -39,7 +39,6 @@
#define TLK_VA_TRANSLATE (0x32000004 | (ULL(1) << 31))
#define TLK_SUSPEND_DONE (0x32000005 | (ULL(1) << 31))
#define TLK_RESUME_DONE (0x32000006 | (ULL(1) << 31))
-#define TLK_SYSTEM_OFF_DONE (0x32000007 | (ULL(1) << 31))
#define TLK_IRQ_DONE (0x32000008 | (ULL(1) << 31))
/*
diff --git a/include/drivers/rpi3/gpio/rpi3_gpio.h b/include/drivers/rpi3/gpio/rpi3_gpio.h
index 159a2e0..7bb3ee2 100644
--- a/include/drivers/rpi3/gpio/rpi3_gpio.h
+++ b/include/drivers/rpi3/gpio/rpi3_gpio.h
@@ -11,11 +11,7 @@
#include <stdint.h>
#include <drivers/gpio.h>
-struct rpi3_gpio_params {
- uintptr_t reg_base;
-};
-
-void rpi3_gpio_init(struct rpi3_gpio_params *params);
+void rpi3_gpio_init(void);
int rpi3_gpio_get_select(int gpio);
void rpi3_gpio_set_select(int gpio, int fsel);
diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h
index 02657a0..b98abdf 100644
--- a/include/lib/cpus/aarch64/denver.h
+++ b/include/lib/cpus/aarch64/denver.h
@@ -34,6 +34,11 @@
#define DENVER_CPU_PMSTATE_C7 U(0x7)
#define DENVER_CPU_PMSTATE_MASK U(0xF)
+/* ACTRL_ELx bits to enable dual execution*/
+#define DENVER_CPU_ENABLE_DUAL_EXEC_EL2 (ULL(1) << 9)
+#define DENVER_CPU_ENABLE_DUAL_EXEC_EL3 (ULL(1) << 9)
+#define DENVER_CPU_ENABLE_DUAL_EXEC_EL1 (U(1) << 4)
+
#ifndef __ASSEMBLER__
/* Disable Dynamic Code Optimisation */
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 6c2925a..a84047a 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -148,6 +148,12 @@
#define ARM_ROTPK_DEVEL_RSA_ID 2
#define ARM_ROTPK_DEVEL_ECDSA_ID 3
+/* Defines used to retrieve ARM SOC revision */
+#define ARM_SOC_CONTINUATION_CODE U(0x4)
+#define ARM_SOC_IDENTIFICATION_CODE U(0x3B)
+#define ARM_SOC_CONTINUATION_SHIFT U(24)
+#define ARM_SOC_IDENTIFICATION_SHIFT U(16)
+
/* IO storage utility functions */
int arm_io_setup(void);
@@ -323,4 +329,7 @@
void plat_arm_secure_wdt_start(void);
void plat_arm_secure_wdt_stop(void);
+/* Get SOC-ID of ARM platform */
+uint32_t plat_arm_get_soc_id(void);
+
#endif /* PLAT_ARM_H */
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index 5b5ebb9..e4431d2 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -322,4 +322,14 @@
*/
unsigned int platform_core_pos_helper(unsigned long mpidr);
+/*
+ * Optional function to get SOC version
+ */
+int32_t plat_get_soc_version(void);
+
+/*
+ * Optional function to get SOC revision
+ */
+int32_t plat_get_soc_revision(void);
+
#endif /* PLATFORM_H */
diff --git a/include/services/arm_arch_svc.h b/include/services/arm_arch_svc.h
index 1cb2038..5bbd8bb 100644
--- a/include/services/arm_arch_svc.h
+++ b/include/services/arm_arch_svc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,7 +9,11 @@
#define SMCCC_VERSION U(0x80000000)
#define SMCCC_ARCH_FEATURES U(0x80000001)
+#define SMCCC_ARCH_SOC_ID U(0x80000002)
#define SMCCC_ARCH_WORKAROUND_1 U(0x80008000)
#define SMCCC_ARCH_WORKAROUND_2 U(0x80007FFF)
+#define SMCCC_GET_SOC_VERSION U(0)
+#define SMCCC_GET_SOC_REVISION U(1)
+
#endif /* ARM_ARCH_SVC_H */
diff --git a/plat/arm/board/fvp/fdts/fvp_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
index 9a4a057..61bd69c 100644
--- a/plat/arm/board/fvp/fdts/fvp_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
@@ -39,7 +39,7 @@
tos_fw-config {
load-address = <0x0 0x04001200>;
- max-size = <0x200>;
+ max-size = <0x1000>;
id = <TOS_FW_CONFIG_ID>;
};
@@ -102,12 +102,12 @@
secure-partitions {
compatible = "arm,sp";
- cactus {
+ cactus-primary {
uuid = <0x1e67b5b4 0xe14f904a 0x13fb1fb8 0xcbdae1da>;
load-address = <0x7000000>;
};
- ivy {
+ cactus-secondary {
uuid = <0x092358d1 0xb94723f0 0x64447c82 0xc88f57f5>;
load-address = <0x7100000>;
};
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
index db3fb55..79c4c07 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
@@ -6,7 +6,7 @@
/dts-v1/;
/ {
- compatible = "spci-core-manifest-1.0";
+ compatible = "arm,spci-core-manifest-1.0";
attribute {
spmc_id = <0x8000>;
@@ -16,4 +16,52 @@
load_address = <0x0 0x6000000>;
entrypoint = <0x0 0x6000000>;
};
+
+ chosen {
+ linux,initrd-start = <0>;
+ linux,initrd-end = <0>;
+ };
+
+ hypervisor {
+ compatible = "hafnium,hafnium";
+ vm1 {
+ is_spci_partition;
+ debug_name = "cactus-primary";
+ load-addr = <0x7000000>;
+ };
+ vm2 {
+ is_spci_partition;
+ debug_name = "cactus-secondary";
+ load-addr = <0x7100000>;
+ vcpu_count = <2>;
+ mem_size = <1048576>;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <0x2>;
+ };
+ };
+ };
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <0xc>;
+ phandle = <0x2>;
+ };
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x6000000 0x2000000>; /* Trusted DRAM */
+ };
};
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 33f3067..c5fae56 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -135,7 +135,7 @@
ARM_SPM_BUF_EL3_MMAP,
#endif
/* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */
- ARM_MAP_NS_DRAM1,
+ ARM_DTB_DRAM_NS,
{0}
};
@@ -163,7 +163,7 @@
MAP_DEVICE0,
MAP_DEVICE1,
/* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */
- ARM_MAP_NS_DRAM1,
+ ARM_DTB_DRAM_NS,
{0}
};
#endif
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 69d49ba..1f569c2 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -52,6 +52,13 @@
#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
#define PLAT_ARM_DRAM2_SIZE UL(0x80000000)
+#define PLAT_HW_CONFIG_DTB_BASE ULL(0x82000000)
+#define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000)
+
+#define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \
+ PLAT_HW_CONFIG_DTB_BASE, \
+ PLAT_HW_CONFIG_DTB_SIZE, \
+ MT_MEMORY | MT_RO | MT_NS)
/*
* Load address of BL33 for this platform port
*/
@@ -70,14 +77,14 @@
# else
# define PLAT_ARM_MMAP_ENTRIES 9
# if USE_DEBUGFS
-# define MAX_XLAT_TABLES 6
+# define MAX_XLAT_TABLES 8
# else
-# define MAX_XLAT_TABLES 5
+# define MAX_XLAT_TABLES 7
# endif
# endif
#elif defined(IMAGE_BL32)
# define PLAT_ARM_MMAP_ENTRIES 9
-# define MAX_XLAT_TABLES 5
+# define MAX_XLAT_TABLES 6
#elif !USE_ROMLIB
# define PLAT_ARM_MMAP_ENTRIES 11
# define MAX_XLAT_TABLES 5
@@ -126,7 +133,7 @@
* calculated using the current BL31 PROGBITS debug size plus the sizes of
* BL2 and BL1-RW
*/
-#define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000)
+#define PLAT_ARM_MAX_BL31_SIZE UL(0x3E000)
#endif /* RESET_TO_BL31 */
#ifndef __aarch64__
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index ca35697..4e20632 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -206,9 +206,11 @@
# Support for fconf in BL31
# Added separately from the above list for better readability
+ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_BL31}),)
BL31_SOURCES += common/fdt_wrappers.c \
lib/fconf/fconf.c \
plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
+endif
ifeq (${FVP_USE_SP804_TIMER},1)
BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
diff --git a/plat/arm/board/fvp/sp_min/sp_min-fvp.mk b/plat/arm/board/fvp/sp_min/sp_min-fvp.mk
index 520a70f..36bf441 100644
--- a/plat/arm/board/fvp/sp_min/sp_min-fvp.mk
+++ b/plat/arm/board/fvp/sp_min/sp_min-fvp.mk
@@ -20,8 +20,10 @@
# Support for fconf in SP_MIN(BL32)
# Added separately from the above list for better readability
+ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_SP_MIN}),)
BL32_SOURCES += common/fdt_wrappers.c \
lib/fconf/fconf.c \
plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
+endif
include plat/arm/common/sp_min/arm_sp_min.mk
diff --git a/plat/arm/board/rddaniel/include/platform_def.h b/plat/arm/board/rddaniel/include/platform_def.h
index 790ed69..a118ca3 100644
--- a/plat/arm/board/rddaniel/include/platform_def.h
+++ b/plat/arm/board/rddaniel/include/platform_def.h
@@ -32,9 +32,19 @@
(n * TZC400_OFFSET))
#define TZC_NSAID_ALL_AP U(0)
+#define TZC_NSAID_PCI U(1)
+#define TZC_NSAID_HDLCD0 U(2)
+#define TZC_NSAID_CLCD U(7)
+#define TZC_NSAID_AP U(9)
+#define TZC_NSAID_VIRTIO U(15)
#define PLAT_ARM_TZC_NS_DEV_ACCESS \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP))
+ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
+ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
+ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \
+ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \
+ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \
+ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c
index d1eee08..60c777e 100644
--- a/plat/arm/common/arm_common.c
+++ b/plat/arm/common/arm_common.c
@@ -25,6 +25,9 @@
* conflicts with the definition in plat/common. */
#pragma weak plat_get_syscnt_freq2
+/* Get ARM SOC-ID */
+#pragma weak plat_arm_get_soc_id
+
/*******************************************************************************
* Changes the memory attributes for the region of mapped memory where the BL
* image's translation tables are located such that the tables will have
@@ -231,3 +234,22 @@
return arm_validate_ns_entrypoint(pa);
}
#endif
+
+/*
+ * Weak function to get ARM platform SOC-ID, Always return SOC-ID=0
+ * ToDo: Get proper SOC-ID for every ARM platform and define this
+ * function separately for every ARM platform.
+ */
+uint32_t plat_arm_get_soc_id(void)
+{
+ return 0U;
+}
+
+/* Get SOC version */
+int32_t plat_get_soc_version(void)
+{
+ return (int32_t)
+ ((ARM_SOC_IDENTIFICATION_CODE << ARM_SOC_IDENTIFICATION_SHIFT)
+ | (ARM_SOC_CONTINUATION_CODE << ARM_SOC_CONTINUATION_SHIFT)
+ | plat_arm_get_soc_id());
+}
diff --git a/plat/common/plat_bl_common.c b/plat/common/plat_bl_common.c
index de6c1d1..d38fc6f 100644
--- a/plat/common/plat_bl_common.c
+++ b/plat/common/plat_bl_common.c
@@ -11,6 +11,7 @@
#include <common/debug.h>
#include <lib/xlat_tables/xlat_tables_compat.h>
#include <plat/common/platform.h>
+#include <smccc_helpers.h>
#include <tools_share/firmware_encrypted.h>
/*
@@ -24,6 +25,18 @@
#pragma weak bl2_plat_handle_post_image_load
#pragma weak plat_try_next_boot_source
#pragma weak plat_get_enc_key_info
+#pragma weak plat_get_soc_version
+#pragma weak plat_get_soc_revision
+
+int32_t plat_get_soc_version(void)
+{
+ return SMC_ARCH_CALL_NOT_SUPPORTED;
+}
+
+int32_t plat_get_soc_revision(void)
+{
+ return SMC_ARCH_CALL_NOT_SUPPORTED;
+}
void bl2_el3_plat_prepare_exit(void)
{
diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
index 7cba3a4..5f01416 100644
--- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
+++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
@@ -39,6 +39,7 @@
.globl plat_crash_console_init
.globl plat_crash_console_putc
.globl plat_crash_console_flush
+ .weak plat_core_pos_by_mpidr
.globl tegra_secure_entrypoint
.globl plat_reset_handler
@@ -140,17 +141,14 @@
* unsigned int plat_my_core_pos(void);
*
* result: CorePos = CoreId + (ClusterId * cpus per cluster)
+ * Registers clobbered: x0, x8
* ----------------------------------------------------------
*/
func plat_my_core_pos
+ mov x8, x30
mrs x0, mpidr_el1
- and x1, x0, #MPIDR_CPU_MASK
- and x0, x0, #MPIDR_CLUSTER_MASK
- lsr x0, x0, #MPIDR_AFFINITY_BITS
- mov x2, #PLATFORM_MAX_CPUS_PER_CLUSTER
- mul x0, x0, x2
- add x0, x1, x0
- ret
+ bl plat_core_pos_by_mpidr
+ ret x8
endfunc plat_my_core_pos
/* -----------------------------------------------------
@@ -273,6 +271,42 @@
ret
endfunc plat_reset_handler
+ /* ------------------------------------------------------
+ * int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
+ *
+ * This function implements a part of the critical
+ * interface between the psci generic layer and the
+ * platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error
+ * code (-1) is returned in case the MPIDR is invalid.
+ *
+ * Clobbers: x0-x3
+ * ------------------------------------------------------
+ */
+func plat_core_pos_by_mpidr
+ lsr x1, x0, #MPIDR_AFF0_SHIFT
+ and x1, x1, #MPIDR_AFFLVL_MASK /* core id */
+ lsr x2, x0, #MPIDR_AFF1_SHIFT
+ and x2, x2, #MPIDR_AFFLVL_MASK /* cluster id */
+
+ /* core_id >= PLATFORM_MAX_CPUS_PER_CLUSTER */
+ mov x0, #-1
+ cmp x1, #(PLATFORM_MAX_CPUS_PER_CLUSTER - 1)
+ b.gt 1f
+
+ /* cluster_id >= PLATFORM_CLUSTER_COUNT */
+ cmp x2, #(PLATFORM_CLUSTER_COUNT - 1)
+ b.gt 1f
+
+ /* CorePos = CoreId + (ClusterId * cpus per cluster) */
+ mov x3, #PLATFORM_MAX_CPUS_PER_CLUSTER
+ mul x3, x3, x2
+ add x0, x1, x3
+
+1:
+ ret
+endfunc plat_core_pos_by_mpidr
+
/* ----------------------------------------
* Secure entrypoint function for CPU boot
* ----------------------------------------
diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk
index 50c9592..66d037f 100644
--- a/plat/nvidia/tegra/common/tegra_common.mk
+++ b/plat/nvidia/tegra/common/tegra_common.mk
@@ -32,5 +32,4 @@
${COMMON_DIR}/tegra_io_storage.c \
${COMMON_DIR}/tegra_platform.c \
${COMMON_DIR}/tegra_pm.c \
- ${COMMON_DIR}/tegra_sip_calls.c \
- ${COMMON_DIR}/tegra_topology.c
+ ${COMMON_DIR}/tegra_sip_calls.c
diff --git a/plat/nvidia/tegra/common/tegra_topology.c b/plat/nvidia/tegra/common/tegra_topology.c
deleted file mode 100644
index 205b051..0000000
--- a/plat/nvidia/tegra/common/tegra_topology.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform_def.h>
-
-#include <arch.h>
-#include <lib/psci/psci.h>
-#include <plat/common/platform.h>
-
-#pragma weak plat_core_pos_by_mpidr
-
-/*******************************************************************************
- * This function implements a part of the critical interface between the psci
- * generic layer and the platform that allows the former to query the platform
- * to convert an MPIDR to a unique linear index. An error code (-1) is returned
- * in case the MPIDR is invalid.
- ******************************************************************************/
-int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
-{
- u_register_t cluster_id, cpu_id;
- int32_t result;
-
- cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) &
- (u_register_t)MPIDR_AFFLVL_MASK;
- cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) &
- (u_register_t)MPIDR_AFFLVL_MASK;
-
- /* CorePos = CoreId + (ClusterId * cpus per cluster) */
- result = (int32_t)cpu_id + ((int32_t)cluster_id *
- PLATFORM_MAX_CPUS_PER_CLUSTER);
-
- if (cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) {
- result = PSCI_E_NOT_PRESENT;
- }
-
- /*
- * Validate cpu_id by checking whether it represents a CPU in
- * one of the two clusters present on the platform.
- */
- if (cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER) {
- result = PSCI_E_NOT_PRESENT;
- }
-
- return result;
-}
diff --git a/plat/nvidia/tegra/include/t186/tegra186_private.h b/plat/nvidia/tegra/include/t186/tegra186_private.h
index 60174ab..4514e14 100644
--- a/plat/nvidia/tegra/include/t186/tegra186_private.h
+++ b/plat/nvidia/tegra/include/t186/tegra186_private.h
@@ -7,10 +7,6 @@
#ifndef TEGRA186_PRIVATE_H
#define TEGRA186_PRIVATE_H
-void tegra186_cpu_reset_handler(void);
-uint64_t tegra186_get_cpu_reset_handler_base(void);
-uint64_t tegra186_get_cpu_reset_handler_size(void);
-uint64_t tegra186_get_mc_ctx_offset(void);
-void tegra186_set_system_suspend_entry(void);
+uint64_t tegra186_get_mc_ctx_size(void);
#endif /* TEGRA186_PRIVATE_H */
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index ad3cee4..f72c9cf 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -47,6 +47,8 @@
uint64_t sc7entry_fw_size;
/* System Suspend Entry Firmware base address */
uint64_t sc7entry_fw_base;
+ /* Enable dual execution */
+ uint8_t enable_ccplex_lock_step;
} plat_params_from_bl2_t;
/*******************************************************************************
diff --git a/plat/nvidia/tegra/platform.mk b/plat/nvidia/tegra/platform.mk
index d0ed5d5..14b9913 100644
--- a/plat/nvidia/tegra/platform.mk
+++ b/plat/nvidia/tegra/platform.mk
@@ -13,7 +13,7 @@
# enable assert() for release/debug builds
ENABLE_ASSERTIONS := 1
-PLAT_LOG_LEVEL_ASSERT := 40
+PLAT_LOG_LEVEL_ASSERT := 50
$(eval $(call add_define,PLAT_LOG_LEVEL_ASSERT))
# enable dynamic memory mapping
diff --git a/plat/nvidia/tegra/soc/t186/drivers/se/se.c b/plat/nvidia/tegra/soc/t186/drivers/se/se.c
index dfb9de8..25f8cd0 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/se/se.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/se/se.c
@@ -12,7 +12,6 @@
#include <bpmp_ipc.h>
#include <pmc.h>
#include <security_engine.h>
-#include <tegra186_private.h>
#include <tegra_private.h>
#include "se_private.h"
diff --git a/plat/nvidia/tegra/soc/t186/plat_memctrl.c b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
index 09377bb..7ff7e77 100644
--- a/plat/nvidia/tegra/soc/t186/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
@@ -10,8 +10,8 @@
#include <mce.h>
#include <memctrl_v2.h>
-#include <tegra_mc_def.h>
#include <tegra186_private.h>
+#include <tegra_mc_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
@@ -711,13 +711,6 @@
void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
{
uint32_t val;
- uint64_t src_base_tzdram;
- const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
- uint64_t src_len_in_bytes = BL31_END - BL31_START;
-
- /* base address of BL3-1 source in TZDRAM */
- src_base_tzdram = params_from_bl2->tzdram_base +
- tegra186_get_cpu_reset_handler_size();
/*
* Setup the Memory controller to allow only secure accesses to
@@ -747,15 +740,6 @@
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_HI, val);
/*
- * save tzdram_addr_lo and ATF-size, this would be used in SC7-RF to
- * generate SHA256.
- */
- mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV68_LO,
- (uint32_t)src_base_tzdram);
- mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV0_HI,
- (uint32_t)src_len_in_bytes);
-
- /*
* MCE propagates the security configuration values across the
* CCPLEX.
*/
diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
index 179dd96..6f58427 100644
--- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
@@ -134,8 +134,7 @@
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val);
/* save MC context to TZDRAM */
- mc_ctx_base = params_from_bl2->tzdram_base +
- tegra186_get_mc_ctx_offset();
+ mc_ctx_base = params_from_bl2->tzdram_base;
tegra_mc_save_context((uintptr_t)mc_ctx_base);
/* Prepare for system suspend */
@@ -158,9 +157,6 @@
(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
(uint64_t)TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U);
- /* set system suspend state for house-keeping */
- tegra186_set_system_suspend_entry();
-
} else {
; /* do nothing */
}
@@ -289,7 +285,7 @@
if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
val = params_from_bl2->tzdram_base +
- tegra186_get_cpu_reset_handler_size();
+ tegra186_get_mc_ctx_size();
/* Initialise communication channel with BPMP */
assert(tegra_bpmp_ipc_init() == 0);
@@ -316,10 +312,19 @@
* BL3-1 over to TZDRAM.
*/
val = params_from_bl2->tzdram_base +
- tegra186_get_cpu_reset_handler_size();
+ tegra186_get_mc_ctx_size();
memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE,
(uintptr_t)BL31_END - (uintptr_t)BL31_BASE);
+ /*
+ * Save code base and size; this would be used by SC7-RF to
+ * verify binary
+ */
+ mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV68_LO,
+ (uint32_t)val);
+ mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV0_HI,
+ (uint32_t)src_len_in_bytes);
+
ret = tegra_bpmp_ipc_disable_clock(TEGRA186_CLK_SE);
if (ret != 0) {
ERROR("Failed to disable clock\n");
diff --git a/plat/nvidia/tegra/soc/t186/plat_secondary.c b/plat/nvidia/tegra/soc/t186/plat_secondary.c
index 1650809..fbb550a 100644
--- a/plat/nvidia/tegra/soc/t186/plat_secondary.c
+++ b/plat/nvidia/tegra/soc/t186/plat_secondary.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,56 +12,30 @@
#include <lib/mmio.h>
#include <mce.h>
-#include <tegra186_private.h>
#include <tegra_def.h>
#include <tegra_private.h>
-#define MISCREG_AA64_RST_LOW 0x2004U
-#define MISCREG_AA64_RST_HIGH 0x2008U
-
#define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658U
#define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65CU
#define CPU_RESET_MODE_AA64 1U
-extern void memcpy16(void *dest, const void *src, unsigned int length);
-
/*******************************************************************************
* Setup secondary CPU vectors
******************************************************************************/
void plat_secondary_setup(void)
{
uint32_t addr_low, addr_high;
- const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
- uint64_t cpu_reset_handler_base, cpu_reset_handler_size;
INFO("Setting up secondary CPU boot\n");
- /*
- * The BL31 code resides in the TZSRAM which loses state
- * when we enter System Suspend. Copy the wakeup trampoline
- * code to TZDRAM to help us exit from System Suspend.
- */
- cpu_reset_handler_base = tegra186_get_cpu_reset_handler_base();
- cpu_reset_handler_size = tegra186_get_cpu_reset_handler_size();
- (void)memcpy16((void *)(uintptr_t)params_from_bl2->tzdram_base,
- (const void *)(uintptr_t)cpu_reset_handler_base,
- cpu_reset_handler_size);
-
/* TZDRAM base will be used as the "resume" address */
- addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64;
- addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU);
-
- /* write lower 32 bits first, then the upper 11 bits */
- mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low);
- mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high);
+ addr_low = (uintptr_t)&tegra_secure_entrypoint | CPU_RESET_MODE_AA64;
+ addr_high = (uintptr_t)(((uintptr_t)&tegra_secure_entrypoint >> 32U) & 0x7ffU);
/* save reset vector to be used during SYSTEM_SUSPEND exit */
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO,
addr_low);
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI,
addr_high);
-
- /* update reset vector address to the CCPLEX */
- (void)mce_update_reset_vector();
}
diff --git a/plat/nvidia/tegra/soc/t186/plat_trampoline.S b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
index 818c24b..2fc2046 100644
--- a/plat/nvidia/tegra/soc/t186/plat_trampoline.S
+++ b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
@@ -12,135 +12,30 @@
#include <plat/common/common_def.h>
#include <tegra_def.h>
-#define TEGRA186_STATE_SYSTEM_SUSPEND 0x5C7
-#define TEGRA186_STATE_SYSTEM_RESUME 0x600D
#define TEGRA186_MC_CTX_SIZE 0x93
- .globl tegra186_cpu_reset_handler
-
-/* CPU reset handler routine */
-func tegra186_cpu_reset_handler _align=4
- /* check if we are exiting system suspend state */
- adr x0, __tegra186_system_suspend_state
- ldr x1, [x0]
- mov x2, #TEGRA186_STATE_SYSTEM_SUSPEND
- lsl x2, x2, #16
- add x2, x2, #TEGRA186_STATE_SYSTEM_SUSPEND
- cmp x1, x2
- bne boot_cpu
-
- /* set system resume state */
- mov x1, #TEGRA186_STATE_SYSTEM_RESUME
- lsl x1, x1, #16
- mov x2, #TEGRA186_STATE_SYSTEM_RESUME
- add x1, x1, x2
- str x1, [x0]
- dsb sy
-
- /* prepare to relocate to TZSRAM */
- mov x0, #BL31_BASE
- adr x1, __tegra186_cpu_reset_handler_end
- adr x2, __tegra186_cpu_reset_handler_data
- ldr x2, [x2, #8]
-
- /* memcpy16 */
-m_loop16:
- cmp x2, #16
- b.lt m_loop1
- ldp x3, x4, [x1], #16
- stp x3, x4, [x0], #16
- sub x2, x2, #16
- b m_loop16
- /* copy byte per byte */
-m_loop1:
- cbz x2, boot_cpu
- ldrb w3, [x1], #1
- strb w3, [x0], #1
- subs x2, x2, #1
- b.ne m_loop1
-
-boot_cpu:
- adr x0, __tegra186_cpu_reset_handler_data
- ldr x0, [x0]
- br x0
-endfunc tegra186_cpu_reset_handler
+ .globl tegra186_get_mc_ctx_size
/*
- * Tegra186 reset data (offset 0x0 - 0x430)
+ * Tegra186 reset data (offset 0x0 - 0x420)
*
- * 0x000: secure world's entrypoint
- * 0x008: BL31 size (RO + RW)
- * 0x00C: MC context start
- * 0x42C: MC context end
+ * 0x000: MC context start
+ * 0x420: MC context end
*/
.align 4
- .type __tegra186_cpu_reset_handler_data, %object
- .globl __tegra186_cpu_reset_handler_data
-__tegra186_cpu_reset_handler_data:
- .quad tegra_secure_entrypoint
- .quad __BL31_END__ - BL31_BASE
-
- .globl __tegra186_system_suspend_state
-__tegra186_system_suspend_state:
- .quad 0
-
- .align 4
- .globl __tegra186_mc_context
__tegra186_mc_context:
.rept TEGRA186_MC_CTX_SIZE
.quad 0
.endr
- .size __tegra186_cpu_reset_handler_data, \
- . - __tegra186_cpu_reset_handler_data
.align 4
- .globl __tegra186_cpu_reset_handler_end
-__tegra186_cpu_reset_handler_end:
-
- .globl tegra186_get_cpu_reset_handler_size
- .globl tegra186_get_cpu_reset_handler_base
- .globl tegra186_get_mc_ctx_offset
- .globl tegra186_set_system_suspend_entry
-
-/* return size of the CPU reset handler */
-func tegra186_get_cpu_reset_handler_size
- adr x0, __tegra186_cpu_reset_handler_end
- adr x1, tegra186_cpu_reset_handler
- sub x0, x0, x1
- ret
-endfunc tegra186_get_cpu_reset_handler_size
-
-/* return the start address of the CPU reset handler */
-func tegra186_get_cpu_reset_handler_base
- adr x0, tegra186_cpu_reset_handler
- ret
-endfunc tegra186_get_cpu_reset_handler_base
+__tegra186_mc_context_end:
/* return the size of the MC context */
-func tegra186_get_mc_ctx_offset
- adr x0, __tegra186_mc_context
- adr x1, tegra186_cpu_reset_handler
+func tegra186_get_mc_ctx_size
+ adr x0, __tegra186_mc_context_end
+ adr x1, __tegra186_mc_context
sub x0, x0, x1
ret
-endfunc tegra186_get_mc_ctx_offset
-
-/* set system suspend state before SC7 entry */
-func tegra186_set_system_suspend_entry
- mov x0, #TEGRA_MC_BASE
- mov x3, #MC_SECURITY_CFG3_0
- ldr w1, [x0, x3]
- lsl x1, x1, #32
- mov x3, #MC_SECURITY_CFG0_0
- ldr w2, [x0, x3]
- orr x3, x1, x2 /* TZDRAM base */
- adr x0, __tegra186_system_suspend_state
- adr x1, tegra186_cpu_reset_handler
- sub x2, x0, x1 /* offset in TZDRAM */
- mov x0, #TEGRA186_STATE_SYSTEM_SUSPEND
- lsl x0, x0, #16
- add x0, x0, #TEGRA186_STATE_SYSTEM_SUSPEND
- str x0, [x3, x2] /* set value in TZDRAM */
- dsb sy
- ret
-endfunc tegra186_set_system_suspend_entry
+endfunc tegra186_get_mc_ctx_size
diff --git a/plat/nvidia/tegra/soc/t186/platform_t186.mk b/plat/nvidia/tegra/soc/t186/platform_t186.mk
index d79155f..c17dab2 100644
--- a/plat/nvidia/tegra/soc/t186/platform_t186.mk
+++ b/plat/nvidia/tegra/soc/t186/platform_t186.mk
@@ -14,7 +14,7 @@
RESET_TO_BL31 := 1
-PROGRAMMABLE_RESET_ADDRESS := 1
+PROGRAMMABLE_RESET_ADDRESS := 0
COLD_BOOT_SINGLE_CPU := 1
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
index 9ccb823..7a68a43 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
@@ -7,6 +7,8 @@
#ifndef T194_NVG_H
#define T194_NVG_H
+#include <lib/utils_def.h>
+
/**
* t194_nvg.h - Header for the NVIDIA Generic interface (NVG).
* Official documentation for this interface is included as part
@@ -20,7 +22,7 @@
*/
enum {
TEGRA_NVG_VERSION_MAJOR = U(6),
- TEGRA_NVG_VERSION_MINOR = U(6)
+ TEGRA_NVG_VERSION_MINOR = U(7)
};
typedef enum {
@@ -71,6 +73,9 @@
TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = U(77),
TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = U(78),
TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = U(79),
+ TEGRA_NVG_CHANNEL_RT_SAFE_MASK = U(80),
+ TEGRA_NVG_CHANNEL_RT_WINDOW_US = U(81),
+ TEGRA_NVG_CHANNEL_RT_FWD_PROGRESS_US = U(82),
TEGRA_NVG_CHANNEL_LAST_INDEX
} tegra_nvg_channel_id_t;
@@ -153,7 +158,7 @@
typedef union {
uint64_t flat;
- struct nvg_power_perf_channel_t {
+ struct {
uint32_t perf_per_watt : U(1);
uint32_t reserved_31_1 : U(31);
uint32_t reserved_63_32 : U(32);
@@ -162,7 +167,7 @@
typedef union {
uint64_t flat;
- struct nvg_power_modes_channel_t {
+ struct {
uint32_t low_battery : U(1);
uint32_t reserved_1_1 : U(1);
uint32_t battery_save : U(1);
@@ -182,7 +187,7 @@
typedef union {
uint64_t flat;
- struct nvg_ccplex_cache_control_channel_t {
+ struct {
uint32_t gpu_ways : U(5);
uint32_t reserved_7_5 : U(3);
uint32_t gpu_only_ways : U(5);
@@ -203,7 +208,7 @@
typedef union {
uint64_t flat;
- struct nvg_wake_time_channel_t {
+ struct {
uint32_t wake_time : U(32);
uint32_t reserved_63_32 : U(32);
} bits;
@@ -211,7 +216,7 @@
typedef union {
uint64_t flat;
- struct nvg_cstate_info_channel_t {
+ struct {
uint32_t cluster_state : U(3);
uint32_t reserved_6_3 : U(4);
uint32_t update_cluster : U(1);
@@ -242,7 +247,7 @@
typedef union {
uint64_t flat;
- struct nvg_lower_bound_channel_t {
+ struct {
uint32_t crossover_value : U(32);
uint32_t reserved_63_32 : U(32);
} bits;
@@ -250,7 +255,7 @@
typedef union {
uint64_t flat;
- struct nvg_cstate_stat_query_channel_t {
+ struct {
uint32_t unit_id : U(4);
uint32_t reserved_15_4 : U(12);
uint32_t stat_id : U(16);
@@ -260,7 +265,7 @@
typedef union {
uint64_t flat;
- struct nvg_num_cores_channel_t {
+ struct {
uint32_t num_cores : U(4);
uint32_t reserved_31_4 : U(28);
uint32_t reserved_63_32 : U(32);
@@ -269,7 +274,7 @@
typedef union {
uint64_t flat;
- struct nvg_unique_logical_id_channel_t {
+ struct {
uint32_t unique_core_id : U(3);
uint32_t reserved_31_3 : U(29);
uint32_t reserved_63_32 : U(32);
@@ -278,7 +283,7 @@
typedef union {
uint64_t flat;
- struct nvg_logical_to_physical_mappings_channel_t {
+ struct {
uint32_t lcore0_pcore_id : U(4);
uint32_t lcore1_pcore_id : U(4);
uint32_t lcore2_pcore_id : U(4);
@@ -306,7 +311,7 @@
typedef union {
uint64_t flat;
- struct nvg_is_sc7_allowed_channel_t {
+ struct {
uint32_t is_sc7_allowed : U(1);
uint32_t reserved_31_1 : U(31);
uint32_t reserved_63_32 : U(32);
@@ -315,7 +320,7 @@
typedef union {
uint64_t flat;
- struct nvg_core_online_channel_t {
+ struct {
uint32_t core_id : U(4);
uint32_t reserved_31_4 : U(28);
uint32_t reserved_63_32 : U(32);
@@ -324,7 +329,7 @@
typedef union {
uint64_t flat;
- struct nvg_cc3_control_channel_t {
+ struct {
uint32_t freq_req : U(9);
uint32_t reserved_30_9 : U(22);
uint32_t enable : U(1);
@@ -374,7 +379,7 @@
typedef union {
uint64_t flat;
- struct nvg_update_ccplex_gsc_channel_t {
+ struct {
uint32_t gsc_enum : U(16);
uint32_t reserved_31_16 : U(16);
uint32_t reserved_63_32 : U(32);
@@ -411,7 +416,7 @@
typedef union {
uint64_t flat;
- struct nvg_hsm_error_ctrl_channel_t {
+ struct {
uint32_t uncorr : U(1);
uint32_t corr : U(1);
uint32_t reserved_31_2 : U(30);
diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
index d92025b..ce5815b 100644
--- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
@@ -368,7 +368,11 @@
int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
+ const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
+ uint8_t enable_ccplex_lock_step = params_from_bl2->enable_ccplex_lock_step;
uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL];
+ cpu_context_t *ctx = cm_get_context(NON_SECURE);
+ uint64_t actlr_elx;
/*
* Reset power state info for CPUs when onlining, we set
@@ -377,6 +381,10 @@
* will re-init this info from non-secure software when the
* core come online.
*/
+ actlr_elx = read_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1));
+ actlr_elx &= ~DENVER_CPU_PMSTATE_MASK;
+ actlr_elx |= DENVER_CPU_PMSTATE_C1;
+ write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx));
/*
* Check if we are exiting from deep sleep and restore SE
@@ -446,13 +454,23 @@
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
}
+ }
- /*
- * Reset power state info for the last core doing SC7
- * entry and exit, we set deepest power state as CC7
- * and SC7 for SC7 entry which may not be requested by
- * non-secure SW which controls idle states.
- */
+ /*
+ * Enable dual execution optimized translations for all ELx.
+ */
+ if (enable_ccplex_lock_step != 0U) {
+ actlr_elx = read_actlr_el3();
+ actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL3;
+ write_actlr_el3(actlr_elx);
+
+ actlr_elx = read_actlr_el2();
+ actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL2;
+ write_actlr_el2(actlr_elx);
+
+ actlr_elx = read_actlr_el1();
+ actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL1;
+ write_actlr_el1(actlr_elx);
}
return PSCI_E_SUCCESS;
diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c
index 235fba4..8255540 100644
--- a/plat/nvidia/tegra/soc/t194/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t194/plat_setup.c
@@ -201,6 +201,10 @@
******************************************************************************/
void plat_early_platform_setup(void)
{
+ const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
+ uint8_t enable_ccplex_lock_step = params_from_bl2->enable_ccplex_lock_step;
+ uint64_t actlr_elx;
+
/* sanity check MCE firmware compatibility */
mce_verify_firmware_version();
@@ -250,6 +254,23 @@
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
}
+
+ /*
+ * Enable dual execution optimized translations for all ELx.
+ */
+ if (enable_ccplex_lock_step != 0U) {
+ actlr_elx = read_actlr_el3();
+ actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL3;
+ write_actlr_el3(actlr_elx);
+
+ actlr_elx = read_actlr_el2();
+ actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL2;
+ write_actlr_el2(actlr_elx);
+
+ actlr_elx = read_actlr_el1();
+ actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL1;
+ write_actlr_el1(actlr_elx);
+ }
}
/* Secure IRQs for Tegra194 */
diff --git a/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c b/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c
index 635018d..4860858 100644
--- a/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c
+++ b/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c
@@ -927,17 +927,12 @@
val &= ~ENTROPY_RESET_BIT;
mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEVICES_W, val);
- if (!tegra_chipid_is_t210_b01()) {
-
- /*
- * T210 SE clock source is turned off in kernel, to simplify
- * SE clock source setting, we switch SE clock source to
- * CLK_M, SE_CLK_DIVISOR = 0. T210 B01 SE clock source is
- * always on, so don't need this setting.
- */
- mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_RST_CTL_CLK_SRC_SE,
- SE_CLK_SRC_CLK_M);
- }
+ /*
+ * Switch SE clock source to CLK_M, to make sure SE clock
+ * is on when saving SE context
+ */
+ mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_RST_CTL_CLK_SRC_SE,
+ SE_CLK_SRC_CLK_M);
/* Enable SE clock */
val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_OUT_ENB_V);
diff --git a/plat/rpi/common/include/rpi_shared.h b/plat/rpi/common/include/rpi_shared.h
index de83571..6863438 100644
--- a/plat/rpi/common/include/rpi_shared.h
+++ b/plat/rpi/common/include/rpi_shared.h
@@ -14,7 +14,7 @@
******************************************************************************/
/* Utility functions */
-void rpi3_console_init(unsigned int base_clk_rate);
+void rpi3_console_init(void);
void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size,
uintptr_t code_start, uintptr_t code_limit,
uintptr_t rodata_start, uintptr_t rodata_limit
diff --git a/plat/rpi/common/rpi3_common.c b/plat/rpi/common/rpi3_common.c
index 27281f2..ef88bf1 100644
--- a/plat/rpi/common/rpi3_common.c
+++ b/plat/rpi/common/rpi3_common.c
@@ -13,7 +13,9 @@
#include <common/debug.h>
#include <bl31/interrupt_mgmt.h>
#include <drivers/console.h>
+#include <drivers/rpi3/gpio/rpi3_gpio.h>
#include <drivers/ti/uart/uart_16550.h>
+#include <drivers/arm/pl011.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <rpi_hw.h>
@@ -104,16 +106,33 @@
******************************************************************************/
static console_t rpi3_console;
-void rpi3_console_init(unsigned int base_clk_rate)
+
+static bool rpi3_use_mini_uart(void)
+{
+ return rpi3_gpio_get_select(14) == RPI3_GPIO_FUNC_ALT5;
+}
+
+void rpi3_console_init(void)
{
int console_scope = CONSOLE_FLAG_BOOT;
-#if RPI3_RUNTIME_UART != -1
- console_scope |= CONSOLE_FLAG_RUNTIME;
-#endif
- int rc = console_16550_register(PLAT_RPI3_UART_BASE,
- base_clk_rate,
- PLAT_RPI3_UART_BAUDRATE,
- &rpi3_console);
+ int rc;
+
+ if (RPI3_RUNTIME_UART != -1)
+ console_scope |= CONSOLE_FLAG_RUNTIME;
+
+ rpi3_gpio_init();
+
+ if (rpi3_use_mini_uart())
+ rc = console_16550_register(PLAT_RPI_MINI_UART_BASE,
+ 0,
+ PLAT_RPI_UART_BAUDRATE,
+ &rpi3_console);
+ else
+ rc = console_pl011_register(PLAT_RPI_PL011_UART_BASE,
+ PLAT_RPI_PL011_UART_CLOCK,
+ PLAT_RPI_UART_BAUDRATE,
+ &rpi3_console);
+
if (rc == 0) {
/*
* The crash console doesn't use the multi console API, it uses
diff --git a/plat/rpi/rpi3/aarch64/plat_helpers.S b/plat/rpi/rpi3/aarch64/plat_helpers.S
index 24278bd..ab925b6 100644
--- a/plat/rpi/rpi3/aarch64/plat_helpers.S
+++ b/plat/rpi/rpi3/aarch64/plat_helpers.S
@@ -9,8 +9,6 @@
#include <assert_macros.S>
#include <platform_def.h>
-#include "../include/rpi_hw.h"
-
.globl plat_crash_console_flush
.globl plat_crash_console_init
.globl plat_crash_console_putc
@@ -133,9 +131,9 @@
* ---------------------------------------------
*/
func plat_crash_console_init
- mov_imm x0, PLAT_RPI3_UART_BASE
- mov_imm x1, PLAT_RPI3_UART_CLK_IN_HZ
- mov_imm x2, PLAT_RPI3_UART_BAUDRATE
+ mov_imm x0, PLAT_RPI_MINI_UART_BASE
+ mov x1, xzr
+ mov x2, xzr
b console_16550_core_init
endfunc plat_crash_console_init
@@ -147,7 +145,7 @@
* ---------------------------------------------
*/
func plat_crash_console_putc
- mov_imm x1, PLAT_RPI3_UART_BASE
+ mov_imm x1, PLAT_RPI_MINI_UART_BASE
b console_16550_core_putc
endfunc plat_crash_console_putc
@@ -160,6 +158,6 @@
* ---------------------------------------------
*/
func plat_crash_console_flush
- mov_imm x0, PLAT_RPI3_UART_BASE
+ mov_imm x0, PLAT_RPI_MINI_UART_BASE
b console_16550_core_flush
endfunc plat_crash_console_flush
diff --git a/plat/rpi/rpi3/include/platform_def.h b/plat/rpi/rpi3/include/platform_def.h
index e308f70..9cacd99 100644
--- a/plat/rpi/rpi3/include/platform_def.h
+++ b/plat/rpi/rpi3/include/platform_def.h
@@ -249,9 +249,10 @@
/*
* Serial-related constants.
*/
-#define PLAT_RPI3_UART_BASE RPI3_MINI_UART_BASE
-#define PLAT_RPI3_UART_CLK_IN_HZ RPI3_MINI_UART_CLK_IN_HZ
-#define PLAT_RPI3_UART_BAUDRATE ULL(115200)
+#define PLAT_RPI_MINI_UART_BASE RPI3_MINI_UART_BASE
+#define PLAT_RPI_PL011_UART_BASE RPI3_PL011_UART_BASE
+#define PLAT_RPI_PL011_UART_CLOCK RPI3_PL011_UART_CLOCK
+#define PLAT_RPI_UART_BAUDRATE ULL(115200)
/*
* System counter
diff --git a/plat/rpi/rpi3/include/rpi_hw.h b/plat/rpi/rpi3/include/rpi_hw.h
index 01d5b4a..2aecab3 100644
--- a/plat/rpi/rpi3/include/rpi_hw.h
+++ b/plat/rpi/rpi3/include/rpi_hw.h
@@ -77,11 +77,15 @@
#define RPI3_RNG_INT_MASK_DISABLE U(0x1)
/*
- * Serial port (called 'Mini UART' in the BCM docucmentation).
+ * Serial ports:
+ * 'Mini UART' in the BCM docucmentation is the 8250 compatible UART.
+ * There is also a PL011 UART, multiplexed to the same pins.
*/
#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040)
#define RPI3_MINI_UART_BASE (RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET)
-#define RPI3_MINI_UART_CLK_IN_HZ ULL(500000000)
+#define RPI3_IO_PL011_UART_OFFSET ULL(0x00201000)
+#define RPI3_PL011_UART_BASE (RPI_IO_BASE + RPI3_IO_PL011_UART_OFFSET)
+#define RPI3_PL011_UART_CLOCK ULL(48000000)
/*
* GPIO controller
diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk
index a21a770..a5b8904 100644
--- a/plat/rpi/rpi3/platform.mk
+++ b/plat/rpi/rpi3/platform.mk
@@ -11,6 +11,10 @@
-Iplat/rpi/rpi3/include
PLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \
+ drivers/arm/pl011/aarch64/pl011_console.S \
+ drivers/gpio/gpio.c \
+ drivers/delay_timer/delay_timer.c \
+ drivers/rpi3/gpio/rpi3_gpio.c \
plat/rpi/common/rpi3_common.c \
${XLAT_TABLES_LIB_SRCS}
@@ -29,10 +33,7 @@
drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
- drivers/gpio/gpio.c \
- drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
- drivers/rpi3/gpio/rpi3_gpio.c \
drivers/io/io_block.c \
drivers/mmc/mmc.c \
drivers/rpi3/sdhost/rpi3_sdhost.c \
diff --git a/plat/rpi/rpi3/rpi3_bl1_setup.c b/plat/rpi/rpi3/rpi3_bl1_setup.c
index dcce76e..3ac30e0 100644
--- a/plat/rpi/rpi3/rpi3_bl1_setup.c
+++ b/plat/rpi/rpi3/rpi3_bl1_setup.c
@@ -35,7 +35,7 @@
0x80000000);
/* Initialize the console to provide early debug support */
- rpi3_console_init(PLAT_RPI3_UART_CLK_IN_HZ);
+ rpi3_console_init();
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = BL_RAM_BASE;
diff --git a/plat/rpi/rpi3/rpi3_bl2_setup.c b/plat/rpi/rpi3/rpi3_bl2_setup.c
index 44827c6..db71817 100644
--- a/plat/rpi/rpi3/rpi3_bl2_setup.c
+++ b/plat/rpi/rpi3/rpi3_bl2_setup.c
@@ -24,17 +24,6 @@
/* Data structure which holds the extents of the trusted SRAM for BL2 */
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
-/* rpi3 GPIO setup function. */
-static void rpi3_gpio_setup(void)
-{
- struct rpi3_gpio_params params;
-
- memset(¶ms, 0, sizeof(struct rpi3_gpio_params));
- params.reg_base = RPI3_GPIO_BASE;
-
- rpi3_gpio_init(¶ms);
-}
-
/* Data structure which holds the MMC info */
static struct mmc_device_info mmc_info;
@@ -62,13 +51,13 @@
meminfo_t *mem_layout = (meminfo_t *) arg1;
/* Initialize the console to provide early debug support */
- rpi3_console_init(PLAT_RPI3_UART_CLK_IN_HZ);
+ rpi3_console_init();
/* Enable arch timer */
generic_delay_timer_init();
/* Setup GPIO driver */
- rpi3_gpio_setup();
+ rpi3_gpio_init();
/* Setup the BL2 memory layout */
bl2_tzram_layout = *mem_layout;
diff --git a/plat/rpi/rpi3/rpi3_bl31_setup.c b/plat/rpi/rpi3/rpi3_bl31_setup.c
index 24a5613..5915753 100644
--- a/plat/rpi/rpi3/rpi3_bl31_setup.c
+++ b/plat/rpi/rpi3/rpi3_bl31_setup.c
@@ -72,7 +72,7 @@
{
/* Initialize the console to provide early debug support */
- rpi3_console_init(PLAT_RPI3_UART_CLK_IN_HZ);
+ rpi3_console_init();
/*
* In debug builds, a special value is passed in 'arg1' to verify
diff --git a/plat/rpi/rpi4/aarch64/plat_helpers.S b/plat/rpi/rpi4/aarch64/plat_helpers.S
index 083c30e..fac1b20 100644
--- a/plat/rpi/rpi4/aarch64/plat_helpers.S
+++ b/plat/rpi/rpi4/aarch64/plat_helpers.S
@@ -10,8 +10,6 @@
#include <platform_def.h>
#include <cortex_a72.h>
-#include "../include/rpi_hw.h"
-
.globl plat_crash_console_flush
.globl plat_crash_console_init
.globl plat_crash_console_putc
@@ -135,7 +133,7 @@
* ---------------------------------------------
*/
func plat_crash_console_init
- mov_imm x0, PLAT_RPI3_UART_BASE
+ mov_imm x0, PLAT_RPI_MINI_UART_BASE
mov x1, xzr
mov x2, xzr
b console_16550_core_init
@@ -149,7 +147,7 @@
* ---------------------------------------------
*/
func plat_crash_console_putc
- mov_imm x1, PLAT_RPI3_UART_BASE
+ mov_imm x1, PLAT_RPI_MINI_UART_BASE
b console_16550_core_putc
endfunc plat_crash_console_putc
@@ -162,7 +160,7 @@
* ---------------------------------------------
*/
func plat_crash_console_flush
- mov_imm x0, PLAT_RPI3_UART_BASE
+ mov_imm x0, PLAT_RPI_MINI_UART_BASE
b console_16550_core_flush
endfunc plat_crash_console_flush
diff --git a/plat/rpi/rpi4/include/platform_def.h b/plat/rpi/rpi4/include/platform_def.h
index a9ecdba..6f6bbbe 100644
--- a/plat/rpi/rpi4/include/platform_def.h
+++ b/plat/rpi/rpi4/include/platform_def.h
@@ -126,8 +126,10 @@
/*
* Serial-related constants.
*/
-#define PLAT_RPI3_UART_BASE RPI3_MINI_UART_BASE
-#define PLAT_RPI3_UART_BAUDRATE ULL(115200)
+#define PLAT_RPI_MINI_UART_BASE RPI4_MINI_UART_BASE
+#define PLAT_RPI_PL011_UART_BASE RPI4_PL011_UART_BASE
+#define PLAT_RPI_PL011_UART_CLOCK RPI4_PL011_UART_CLOCK
+#define PLAT_RPI_UART_BAUDRATE ULL(115200)
/*
* System counter
diff --git a/plat/rpi/rpi4/include/rpi_hw.h b/plat/rpi/rpi4/include/rpi_hw.h
index b1dd4e9..7185106 100644
--- a/plat/rpi/rpi4/include/rpi_hw.h
+++ b/plat/rpi/rpi4/include/rpi_hw.h
@@ -77,10 +77,15 @@
#define RPI3_RNG_INT_MASK_DISABLE U(0x1)
/*
- * Serial port (called 'Mini UART' in the Broadcom documentation).
+ * Serial ports:
+ * 'Mini UART' in the BCM docucmentation is the 8250 compatible UART.
+ * There is also a PL011 UART, multiplexed to the same pins.
*/
-#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040)
-#define RPI3_MINI_UART_BASE (RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET)
+#define RPI4_IO_MINI_UART_OFFSET ULL(0x00215040)
+#define RPI4_MINI_UART_BASE (RPI_IO_BASE + RPI4_IO_MINI_UART_OFFSET)
+#define RPI4_IO_PL011_UART_OFFSET ULL(0x00201000)
+#define RPI4_PL011_UART_BASE (RPI_IO_BASE + RPI4_IO_PL011_UART_OFFSET)
+#define RPI4_PL011_UART_CLOCK ULL(48000000)
/*
* GPIO controller
diff --git a/plat/rpi/rpi4/platform.mk b/plat/rpi/rpi4/platform.mk
index 2038021..49e78df 100644
--- a/plat/rpi/rpi4/platform.mk
+++ b/plat/rpi/rpi4/platform.mk
@@ -11,6 +11,7 @@
-Iplat/rpi/rpi4/include
PLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \
+ drivers/arm/pl011/aarch64/pl011_console.S \
plat/rpi/common/rpi3_common.c \
${XLAT_TABLES_LIB_SRCS}
@@ -20,6 +21,9 @@
drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_helpers.c \
drivers/arm/gic/v2/gicv2_main.c \
+ drivers/delay_timer/delay_timer.c \
+ drivers/gpio/gpio.c \
+ drivers/rpi3/gpio/rpi3_gpio.c \
plat/common/plat_gicv2.c \
plat/rpi/rpi4/rpi4_bl31_setup.c \
plat/rpi/common/rpi3_pm.c \
diff --git a/plat/rpi/rpi4/rpi4_bl31_setup.c b/plat/rpi/rpi4/rpi4_bl31_setup.c
index 9e3b539..0a49d81 100644
--- a/plat/rpi/rpi4/rpi4_bl31_setup.c
+++ b/plat/rpi/rpi4/rpi4_bl31_setup.c
@@ -132,14 +132,8 @@
/* Early GPU firmware revisions need a little break here. */
ldelay(100000);
- /*
- * Initialize the console to provide early debug support.
- * We rely on the GPU firmware to have initialised the UART correctly,
- * as the baud base clock rate differs across GPU firmware revisions.
- * Providing a base clock of 0 lets the 16550 UART init routine skip
- * the initial enablement and baud rate setup.
- */
- rpi3_console_init(0);
+ /* Initialize the console to provide early debug support. */
+ rpi3_console_init();
bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
bl33_image_ep_info.spsr = rpi3_get_spsr_for_bl33_entry();
diff --git a/services/arm_arch_svc/arm_arch_svc_setup.c b/services/arm_arch_svc/arm_arch_svc_setup.c
index 6dac56e..ba53930 100644
--- a/services/arm_arch_svc/arm_arch_svc_setup.c
+++ b/services/arm_arch_svc/arm_arch_svc_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,18 +12,27 @@
#include <lib/smccc.h>
#include <services/arm_arch_svc.h>
#include <smccc_helpers.h>
+#include <plat/common/platform.h>
static int32_t smccc_version(void)
{
return MAKE_SMCCC_VERSION(SMCCC_MAJOR_VERSION, SMCCC_MINOR_VERSION);
}
-static int32_t smccc_arch_features(u_register_t arg)
+static int32_t smccc_arch_features(u_register_t arg1, u_register_t arg2)
{
- switch (arg) {
+ switch (arg1) {
case SMCCC_VERSION:
case SMCCC_ARCH_FEATURES:
return SMC_OK;
+ case SMCCC_ARCH_SOC_ID:
+ if (arg2 == SMCCC_GET_SOC_REVISION) {
+ return plat_get_soc_revision();
+ }
+ if (arg2 == SMCCC_GET_SOC_VERSION) {
+ return plat_get_soc_version();
+ }
+ return SMC_ARCH_CALL_INVAL_PARAM;
#if WORKAROUND_CVE_2017_5715
case SMCCC_ARCH_WORKAROUND_1:
if (check_wa_cve_2017_5715() == ERRATA_NOT_APPLIES)
@@ -94,7 +103,7 @@
case SMCCC_VERSION:
SMC_RET1(handle, smccc_version());
case SMCCC_ARCH_FEATURES:
- SMC_RET1(handle, smccc_arch_features(x1));
+ SMC_RET1(handle, smccc_arch_features(x1, x2));
#if WORKAROUND_CVE_2017_5715
case SMCCC_ARCH_WORKAROUND_1:
/*
diff --git a/services/spd/tlkd/tlkd_main.c b/services/spd/tlkd/tlkd_main.c
index 32ae8ec..481bb69 100644
--- a/services/spd/tlkd/tlkd_main.c
+++ b/services/spd/tlkd/tlkd_main.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -429,7 +430,6 @@
*/
case TLK_SUSPEND_DONE:
case TLK_RESUME_DONE:
- case TLK_SYSTEM_OFF_DONE:
if (ns)
SMC_RET1(handle, SMC_UNK);
diff --git a/services/spd/tlkd/tlkd_pm.c b/services/spd/tlkd/tlkd_pm.c
index 7d1959b..ed5bf77 100644
--- a/services/spd/tlkd/tlkd_pm.c
+++ b/services/spd/tlkd/tlkd_pm.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -98,29 +99,6 @@
}
/*******************************************************************************
- * System is about to be reset. Inform the SP to allow any book-keeping
- ******************************************************************************/
-static void system_off_handler(void)
-{
- int cpu = read_mpidr() & MPIDR_CPU_MASK;
- gp_regs_t *gp_regs;
-
- /* TLK runs only on CPU0 */
- if (cpu != 0)
- return;
-
- /* pass system off/reset events to TLK */
- gp_regs = get_gpregs_ctx(&tlk_ctx.cpu_ctx);
- write_ctx_reg(gp_regs, CTX_GPREG_X0, TLK_SYSTEM_OFF);
-
- /*
- * Enter the SP. We do not care about the return value because we
- * must continue with the shutdown anyway.
- */
- (void)tlkd_synchronous_sp_entry(&tlk_ctx);
-}
-
-/*******************************************************************************
* Structure populated by the Dispatcher to be given a chance to perform any
* bookkeeping before PSCI executes a power mgmt. operation.
******************************************************************************/
@@ -128,6 +106,4 @@
.svc_migrate_info = cpu_migrate_info,
.svc_suspend = cpu_suspend_handler,
.svc_suspend_finish = cpu_resume_handler,
- .svc_system_off = system_off_handler,
- .svc_system_reset = system_off_handler
};
diff --git a/services/spd/trusty/trusty.c b/services/spd/trusty/trusty.c
index ba2f4a6..b10da76 100644
--- a/services/spd/trusty/trusty.c
+++ b/services/spd/trusty/trusty.c
@@ -413,7 +413,7 @@
/* Get trusty's entry point info */
ep_info = bl31_plat_get_next_image_ep_info(SECURE);
if (ep_info == NULL) {
- INFO("Trusty image missing.\n");
+ VERBOSE("Trusty image missing.\n");
return -1;
}
@@ -466,7 +466,7 @@
trusty_fiq_handler,
flags);
if (ret != 0) {
- ERROR("trusty: failed to register fiq handler, ret = %d\n", ret);
+ VERBOSE("trusty: failed to register fiq handler, ret = %d\n", ret);
}
if (aarch32) {