xlat v2: Turn MMU parameters into 64-bit values
Most registers are 64-bit wide, even in AArch32 mode:
- MAIR_ELx is equivalent to MAIR0 and MAIR1.
- TTBR is 64 bit in both AArch64 and AArch32.
The only difference is the TCR register, which is 32 bit in AArch32 and
in EL3 in AArch64. For consistency with the rest of ELs in AArch64, it
makes sense to also have it as a 64-bit value.
Change-Id: I2274d66a28876702e7085df5f8aad0e7ec139da9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
diff --git a/lib/xlat_tables_v2/aarch64/enable_mmu.S b/lib/xlat_tables_v2/aarch64/enable_mmu.S
index a72c7fa..5c5a2a9 100644
--- a/lib/xlat_tables_v2/aarch64/enable_mmu.S
+++ b/lib/xlat_tables_v2/aarch64/enable_mmu.S
@@ -43,17 +43,15 @@
ldr x0, =mmu_cfg_params
/* MAIR */
- ldr w1, [x0, #(MMU_CFG_MAIR0 << 2)]
+ ldr x1, [x0, #(MMU_CFG_MAIR << 3)]
_msr mair, \el, x1
/* TCR */
- ldr w2, [x0, #(MMU_CFG_TCR << 2)]
+ ldr x2, [x0, #(MMU_CFG_TCR << 3)]
_msr tcr, \el, x2
/* TTBR */
- ldr w3, [x0, #(MMU_CFG_TTBR0_LO << 2)]
- ldr w4, [x0, #(MMU_CFG_TTBR0_HI << 2)]
- orr x3, x3, x4, lsl #32
+ ldr x3, [x0, #(MMU_CFG_TTBR0 << 3)]
_msr ttbr0, \el, x3
/*