commit 658cb0725f6afa5838736137fec0d6171fbc23b8
author Roger Lu <roger.lu@mediatek.com> Mon Oct 28 21:11:48 2019 +0800
committer kenny liang <kenny.liang@mediatek.com> Tue Nov 05 16:34:26 2019 +0800
tree 6fbf764431fb49f64bbe1f74af08d1cb361b8807
parent 1d2b41614c5675b144ae1f4517c1f8bf249a12d2

mediatek: mt8183: switch PLL/CLKSQ/ck_off/axi_26m control to SPM

1. Switch ARMPLL_LL/CCIPLL/MAINPLL/MPLL control to SPM
2. Switch CLKSQ1/TDCLKSQ control to SPM
3. Switch ck_off/axi_26m control to SPM

BUG=b:136980838
TEST=system suspend/resume passed

Change-Id: I5c8506f7cf16d5cdaeb5ef8caa60a2992a361e18
Signed-off-by: Roger Lu <roger.lu@mediatek.com>

plat/mediatek/mt8183/include/platform_def.h

diff --git a/plat/mediatek/mt8183/include/platform_def.h b/plat/mediatek/mt8183/include/platform_def.h
index 0a1e038..ad81a33 100644
--- a/plat/mediatek/mt8183/include/platform_def.h
+++ b/plat/mediatek/mt8183/include/platform_def.h
@@ -39,7 +39,14 @@
 
 #define INFRACFG_AO_BASE   (IO_PHYS + 0x1000)
 
+#define TOPCKGEN_BASE      (IO_PHYS + 0x0)
+#define CLK_SCP_CFG_0      (TOPCKGEN_BASE + 0x200)
+#define CLK_SCP_CFG_1      (TOPCKGEN_BASE + 0x204)
+
 #define APMIXEDSYS         (IO_PHYS + 0xC000)
+#define AP_PLL_CON3        (APMIXEDSYS + 0xC)
+#define AP_PLL_CON4        (APMIXEDSYS + 0x10)
+#define AP_PLL_CON6        (APMIXEDSYS + 0x18)
 #define ARMPLL_LL_CON0     (APMIXEDSYS + 0x200)
 #define ARMPLL_L_CON0      (APMIXEDSYS + 0x210)
 #define ARMPLL_L_PWR_CON0  (APMIXEDSYS + 0x21c)