feat(imx8mq): add 100us delay after USB OTG SRC bit 0 clear
After the SRC bit clear, we must wait for a while to make sure
the operation is finished. And don't enable all the PU domains
for USB OTG, the limitations are:
1. before system clock configuration. ipg clock runs at 12.5MHz.
delay time should longer than 82us.
2. after system clock configuration. ipg clock runs at 66.5MHz.
delay time should longer than 15.3us.
so add udelay 100 to safely clear the SRC bit 0.
Signed-off-by: Jacky Bai <firstname.lastname@example.org>
1 file changed