fix(cpus): workaround for Cortex-A78C erratum 1827430
Cortex-A78C erratum 1827430 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1.
The workaround is to set the CPUECTLR_EL1[53] to 1, which disables
allocation of splintered pages in the L2 TLB.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1707916/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ie68771bdd3bddeff54d06b6a456dad4a7fc27426
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 8a20186..73c7ac5 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -349,6 +349,10 @@
For Cortex-A78C, the following errata build flags are defined :
+- ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to
+ Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is
+ fixed in r0p1.
+
- ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to
Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
it is still open.